coreboot changelog Jan 27 – Feb 2

This changelog covers 131 commits in the week between January 27, 2016 and February 2, 2016. (dd4b66e2 – 95909924)

The biggest news of the past week was getting the 4.3 release done. The 4.4 release should come towards the end of April.

Of particular note to anyone submitting patches, we added 2 new code checkers this week, one to verify that the executable bit isn’t set on source files, and one to verify that the standard coreboot license header is used on files using the GPL 2 or 2+ licenses. These checks will be run automatically when you commit code if you have the git commit hook in place, and will also be run on the build server.

coreboot again had numerous patches surrounding the build system, tools, and utilities. The flood of cbfstool related patches finally slowed a bit, but we still had some cleanup, both in the tool and in the cbfs sections of the Makefiles. In the toolchain area, we updated LLVM to version 3.7.1, and added GNU Make to the toolchain. The addition of make was to address some upcoming patches that needed the newer version, as well as to support platforms that don’t install GNU make by default. The kconfig_lint tool had various updates to get rid of warnings that we don’t care about, to add documentation, and to add a couple of additional checks. Next week will see a few more fixes, and it will be put in place as a stable lint tool.

We had significant updates to a number of mainboards and the related chipsets in the past week as well. Intel had a large number of changes for their Braswell SoC and its reference board, Strago, merged this week. These included fixes for GPIOs, clocks, SD cards, and thermal support, as well as FSP integration updates. The Asus kgpe-d16 mainboard, along with the AMD Fam10h-Fam15h processor directory and the SB700 soutbridge had numerous patches to improve stability, fix IRQ routing and APIC identification, and improve ACPI. The winbond w83667hg-a was added to the coreboot codebase for the board as well. The Intel d510mo board had some improvements related to native graphics initialization, GPIOs and ACPI. The gigabyte ga-g41m-es2l and the Intel x4x northbridge code had some general cleanup and improvements to cbmem and memory initialization. We also saw the introduction of the initial framework for the new Intel Apollo Lake SoC. We’ll be seeing many more patches related to Apollo Lake in the coming weeks.

Other changes of note included code to initialize the PS/2 aux port, a way to access memory address 0 without GCC “optimizing” it into a crash, and the addition of some documentation from Intel about developing new FSP based boards and chipsets. Finally, the Intel sklrvp Skylake reference board was dropped in favor of using the kunimitsu board.

coreboot statistics for the past week

- Total commits: 131
- New authors: 8
- Total authors: 30
- Total lines added: 3833
- Total lines removed: -3652
- Delta: 181

=== Top Authors - Number of commits ===
Timothy Pearson              22 (16.794%)
Martin Roth                  21 (16.031%)
Patrick Georgi               15 (11.450%)
Damien Zammit                13 (9.924%)
Hannah Williams              12 (9.160%)
Leroy P Leahy                 5 (3.817%)
Stefan Reinauer               5 (3.817%)
Divagar Mohandass             4 (3.053%)
Vladimir Serbinenko           3 (2.290%)
Alexandru Gagniuc             3 (2.290%)
Total Authors: 31

=== Top Authors - Lines added ===
Damien Zammit               725 (18.915%)
Timothy Pearson             701 (18.289%)
Leroy P Leahy               646 (16.854%)
Subrata Banik               427 (11.140%)
Martin Roth                 262 (6.835%)
Aaron Durbin                204 (5.322%)
Patrick Georgi              179 (4.670%)
Alexandru Gagniuc           140 (3.652%)
shkim                       107 (2.792%)
Nico Huber                   91 (2.374%)

=== Top Authors - Lines removed ===
Martin Roth                1688 (46.221%)
Hannah Williams             661 (18.100%)
Divagar Mohandass           315 (8.625%)
Damien Zammit               307 (8.406%)
Timothy Pearson             212 (5.805%)
Patrick Georgi              104 (2.848%)
Nico Huber                  102 (2.793%)
Leroy P Leahy                95 (2.601%)
Stefan Reinauer              43 (1.177%)
Lee Leahy                    23 (0.630%)

=== Top Reviewers - Number of patches reviewed ===
Martin Roth                  71 (54.198%)
Stefan Reinauer              20 (15.267%)
Patrick Georgi               18 (13.740%)
Paul Menzel                  16 (12.214%)
Alexandru Gagniuc            14 (10.687%)
Aaron Durbin                 10 (7.634%)
Felix Held                    8 (6.107%)
Timothy Pearson               7 (5.344%)
Nico Huber                    4 (3.053%)
Alexander Couzens             3 (2.290%)
Total Reviewers: 15

=== Top Submitters - Number of patches merged ===
Martin Roth                  94 (71.756%)
Patrick Georgi               15 (11.450%)
Stefan Reinauer               8 (6.107%)
Leroy P Leahy                 6 (4.580%)
Vladimir Serbinenko           3 (2.290%)
Nico Huber                    2 (1.527%)
Aaron Durbin                  2 (1.527%)
Werner Zeh                    1 (0.763%)
Total Submitters: 8

Announcing coreboot 4.3

The “Oh, has FOSDEM started?” release
Dear coreboot community,

today marks the release of coreboot 4.3, the third release on our time based release schedule.
Since the last release, 1030 commits by 114 authors added a net total of 17500 lines to the source code. Thank you to all who contributed!

The release tarballs are available at http://www.coreboot.org/releases/. There’s also a 4.3 tag and branch in the git repository.

Besides the usual addition of new mainboards (14) and chipsets (various), a big theme of the development since 4.2 was cleaning up the code: 20 mainboards were removed that aren’t on the market for years (and even hard to get on Ebay). For several parts of the tree, we established tighter controls, making errors out of what were warnings (and cleaning up the code to match) and provided better tests for various aspects of the tree, and in general tried to establish a more consistent structure across the code base.

Besides that, we had various improvements across the tree, each important when using the hardware, but to numerous for individual shout outs. Martin compiled a list that’s best posted verbatim. Thanks Martin!

Log of commit 529fd81f640fa514ea4c443dd561086e7c582a64 to commit 1bf5e6409678d04fd15f9625460078853118521c for a total of 1030 commits:

Mainboards

Added 14 mainboards

– asus/kfsn4-dre_k8: Native init Dual AMD K8 CPUs & Nvidia CK804 southbridge
– esd/atom15: Bay Trail SOC mainboard using Intel’s FSP
– gigabyte/ga-g41m-es2l: Intel Core 2 / Native init x4x NB / I82801GX SB
– google/guado: Intel Broadwell chromebox (Asus Chromebox CN62)
– google/oak: Mediatek MT8173 SoC chromebook
– google/tidus: Intel Broadwell chromebox (Lenovo ThinkCentre Chromebox)
– google/veyron_emile: Rockchip RK3288 SoC board
– intel/d510mo: Native init Intel Pineview with Intel I82801GX southbridge
– intel/littleplains: Intel Atom c2000 (Rangeley) SoC board
– intel/stargo2: Intel Ivy Bridge / Cave Creek usint Intel’s FSP
– lenovo/r400: Intel Core 2 / Native init GM45 NB / Intel I82801IX SB
– lenovo/t500: Intel Core 2 / Native init GM45 NB / Intel I82801IX SB
– purism/librem13: Intel Broadwell Laptop using Intel MRC
– sunw/ultra40m2: Native init Dual AMD K8 Processors & Nvidia MCP55 SB

Removed 20 mainboards

– arima/hdama
– digitallogic/adl855pc
– ibm/e325, e326
– intel/sklrvp
– iwill/dk8s2, dk8x
– newisys/khepri
– tyan/s2735, s2850, s2875, s2880, s2881 & s2882
– tyan/s2885, s2891, s2892, s2895, s4880 & s4882

Improvements to mainboards

– amd/bettong: fixes to Interrupts, Memory config, S4, EMMC, UARTS
– asus/kgpe-d16: IOMMU and memory fixes, Add CMOS options, Enable GART
– intel/strago: GPIO, DDR, & SD config, FSP updates, Clock fixes
– ACPI fixes across various platforms
– Many individual fixes to other mainboards

Continued updates for the Intel Skylake platform

– google/chell, glados, & lars: FSP & Memory updates, Add Fan & NHLT support
– intel/kunimitsu: FSP & GPIO updates, Add Fan & NHLT (audio) support

Build system

– Update build to use FMAP based firmware layout with multiple cbfs sections
– Enable Kconfig strict mode – Kconfig warnings are no longer allowed.
– Enable ACPI warnings are errors in IASL – warnings are no longer allowed.
– Tighten checking on toolchains and give feedback to users if there are issues
– Updates to get the ADA compiler to work correctly for coreboot
– Various improvements to Makefiles and build scripts
– Cleanup of CBFS file handling

Utilities

– cleanups and improvements to many of the utilities
– cbfstool: Many fixes and extensions to integrate with FMAP
– Add amdfwtool to combine AMD firmware blobs instead of using shell scripts.
– Toolchain updates: new versions of GMP & MPFR. Add ADA.
– Updates for building on NetBSD & OS X

Payloads

– SeaBIOS: Update stable release to 1.9.0
– coreinfo: fix date, hide cursor, use crosscompiler to build
– libpayload: updates for cbfs, XHCI and DesignWare HCD controllers

ARM

– Added 1 soc: mediatek/mt8173
– Various fixes for ARM64 platforms

X86

– Added 2 northbridges: intel/pineview & x4x
– Removed 1 northbridge: intel/i440lx
– Added 1 southbridge: intel/fsp_i89xx
– Removed 2 southbridge(s): intel/esb6300 & i82801cx
– Rename amd/model_10xxx to family_10h-family_15h.
– ACPI: fix warnings, Add functions for IVRS, DMAR I/O-APIC and HPET entries
– Work in many areas fixing issues compiling in 64-bit
– Numerous other fixes across the tree

Areas with significant work on updates and fixes

– cpu/amd/model_fxx
– intel/fsp1_x: Fix timestanps & postcodes, add native CAR & microcode
– nb/amd/amdfam10: Add S3, voltage & ACPI, speed fixes & MANY other changes
– nb/amd/amdmct: Add S3, mem voltage, Fix performance & MANY other changes
– nb/intel/sandybridge: Add IOMMU & ACPI DMAR support, Memory cleanup
– soc/intel/braswell: FSP & ACPI updates, GPIO & clock Fixes
– soc/intel/fsp_baytrail: GPIO, microcode and Interrupt updates.
– soc/intel/skylake: FSP, Power/Thermal & GPIO Updates, Add NHLT support
– sb/amd/sb700: Add ACPI & CMOS Setting support, SATA & clock Fixes

MIPS

– Imgtec Pistachio: Memory, PLL & I2C fixes, add reset

SuperIO

– Expand functionality for ite/it8718f & nuvoton/nct5572d superio devices

Added 3 SIOs

– intel/i8900
– winbond/w83667hg-a & wpcd376i

Removed 6 SIOs

– fintek/f71889
– ite/it8661f
– nsc/pc8374 & pc97307
– nuvoton/nct6776
– smsc/fdc37m60x

Lib

– Several updates for reading EDID tables

MISC

– Commonlib: continued updates for cbfs changes
– Work on getting license headers on all coreboot files
– Drop the third paragraph of GPL copyright header across all of coreboot

Submodules

3rdparty/blobs: Update to CarrizoPI 1.1.0.1 (Binary PI 1.5)

coreboot statistics

Total commits: 1030
Total authors: 114
New authors: 46
Total Reviewers: 41
Total lines added: 88255
Total lines removed: -70735
Total delta: 17520

coreboot changelog Jan 20 – Jan 26

This changelog covers 111 commits in the week between January 20, 2016 and January 26, 2016. (aad9b6a – 7ee6cd5)

There was another large set of patches continuing the work that has been done extending cbfs and integrating FMAP.  This series is expected to be finished in just a few more patches.

This past week saw the addition of two new mainboards – the Google Tidus board (Lenovo ThinkCentre Chromebox), and the Purism Librem 13 laptop.  Updates to the Google Oak board and its associated SoC, the Mediatek MT8173 Cortex A72, accounted for roughly 20% of this week’s changes.

The AMD native memory initialization for the family10h/family15h chips had more changes, with still more coming next week.  On the Intel side, the Pineview northbridge saw a couple of updates, and there were several fixes for for Intel’s Braswell and Skylake chips.

coreboot also had some more toolchain updates this week, adding an ada compiler for some upcoming work, and getting the gcc build set up for the Power8 work.  There were also a couple of fixes for building tools under NetBSD

In the coming week, we should get the 4.3 release finished, and see a slew of changes as the patches that are currently in review get merged.

coreboot statistics for the past week

- Total commits: 111
- New authors: 11
- Total authors: 36
- Total lines added: 10885
- Total lines removed: -604
- Delta: 10281

=== Authors - Number of commits ===
Patrick Georgi       15 (13.514%)
Martin Roth          11 (9.910%)
Nico Huber            8 (7.207%)
Timothy Pearson       8 (7.207%)
Duncan Laurie         7 (6.306%)
Alexandru Gagniuc     6 (5.405%)
Werner Zeh            5 (4.505%)
Damien Zammit         4 (3.604%)
Itamar                4 (3.604%)
Yidi Lin              3 (2.703%)
Felix Durairaj        3 (2.703%)
Koro Chen             3 (2.703%)
Aaron Durbin          3 (2.703%)
Total Authors: 36

=== Authors - Lines added ===
Matt DeVillier     2456 (22.563%)
Patrick Georgi     1968 (18.080%)
Duncan Laurie      1264 (11.612%)
Timothy Pearson    1260 (11.576%)
Tianping Fang       505 (4.639%)
Liguo Zhang         460 (4.226%)
Leilk Liu           418 (3.840%)
David Hendricks     395 (3.629%)
Chunfeng Yun        368 (3.381%)
Subrata Banik       321 (2.949%)

=== Authors - Lines removed ===
Patrick Georgi      158 (26.159%)
Timothy Pearson     137 (22.682%)
Aaron Durbin         75 (12.417%)
Stefan Reinauer      30 (4.967%)
Martin Roth          25 (4.139%)
Nico Huber           24 (3.974%)
Alexandru Gagniuc    23 (3.808%)
T.H.Lin              21 (3.477%)
Damien Zammit        20 (3.311%)
Duncan Laurie        20 (3.311%)

=== Reviewers - Number of patches reviewed ===
Martin Roth          48 (43.243%)
Stefan Reinauer      28 (25.225%)
Patrick Georgi       26 (23.423%)
Paul Menzel          17 (15.315%)
Alexandru Gagniuc    12 (10.811%)
Aaron Durbin         12 (10.811%)
Ronald G. Minnich     5 (4.505%)
Nico Huber            2 (1.802%)
Timothy Pearson       2 (1.802%)
Felix Held            2 (1.802%)
Total Reviewers: 17

=== Submitters - Number of patches merged ===
Patrick Georgi       58 (52.252%)
Martin Roth          30 (27.027%)
Aaron Durbin          7 (6.306%)
Nico Huber            6 (5.405%)
Werner Zeh            5 (4.505%)
Stefan Reinauer       3 (2.703%)
Duncan Laurie         2 (1.802%)
Total Submitters: 7

coreboot changelog Jan 5 – Jan 19

This changelog covers the 180 commits between January 5, 2016 and
January 19, 2016.  (af91b8b0 – 967881d0)

We’re preparing for the coreboot 4.3 release, expected to happen sometime in the next week, so there has been a lot of activity surrounding Intel’s Skylake chips, both in the mainboards and SOC directories. The Skylake and braswell platforms are finally being build-tested by jenkins, which will help keep the platforms working.

The changes in cbfstool are continuing to roll in, although this should be wrapping up before long as the merger of cbfs with FMAP is completed.

The effort to standardize coreboot’s license headers across all files is just starting, and will be going on for a few weeks as we verify that all source files have the correct headers.  We’ve added and improved the lint checkers for these so expect failures from jenkins if files with non-compliant headers are pushed.

A fair amount of work was done in the build system in the past couple of weeks.  This removed the warnings about cross compilers not existing unless that architecture is currently being built, fixed some dependency issues, and fixed several other minor issues. A make target to check the versions of the coreboot toolchain was also added.

We had a slight toolchain change, going to MPFR version 3.1.3 to fix some issues seen on the upcoming Power8 processor.

Additional changes added NetBSD support for various utilities, and update the intel/gm45 and intel/pineview northbridges.

Added 1 mainboard:
——————-
– google/guado

coreboot statistics
——————-
– Total commits: 180
– New authors: 13
– Total authors: 45
– Total reviewers: 19
– Total lines added: 9168
– Total lines removed: -2130
– Total difference: 7038

=== Authors – Number of commits ===
Martin Roth                  56 (31.111%)
David Wu                     15 (8.333%)
Aaron Durbin                 12 (6.667%)
Duncan Laurie                 9 (5.000%)
Subrata Banik                 8 (4.444%)
Rizwan Qureshi                7 (3.889%)
Nico Huber                    6 (3.333%)
Patrick Georgi                6 (3.333%)
Timothy Pearson               5 (2.778%)
Barnali Sarkar                5 (2.778%)
Total Authors: 45

=== Authors – Lines added ===
Martin Roth                2359 (25.731%)
Matt DeVillier             2243 (24.466%)
Aaron Durbin               1988 (21.684%)
Rizwan Qureshi              606 (6.610%)
Subrata Banik               292 (3.185%)
Barnali Sarkar              178 (1.942%)
robbie zhang                158 (1.723%)
Nico Huber                  144 (1.571%)
Andrey Korolyov             133 (1.451%)
David Wu                    128 (1.396%)

=== Authors – Lines removed ===
Martin Roth                1038 (48.732%)
Barnali Sarkar              173 (8.122%)
Aaron Durbin                144 (6.761%)
Nico Huber                  108 (5.070%)
Patrick Georgi               98 (4.601%)
Shaunak Saha                 81 (3.803%)
Paul Menzel                  69 (3.239%)
Patrick Rudolph              68 (3.192%)
Subrata Banik                64 (3.005%)
Duncan Laurie                61 (2.864%)

=== Reviewers – Number of patches reviewed ===
Martin Roth                  91 (50.556%)
Stefan Reinauer              43 (23.889%)
Patrick Georgi               43 (23.889%)
Paul Menzel                  23 (12.778%)
Alexandru Gagniuc            13 (7.222%)
Nico Huber                    7 (3.889%)
York Yang                     3 (1.667%)
Werner Zeh                    3 (1.667%)
Aaron Durbin                  3 (1.667%)
Total Reviewers: 19

=== Submitters – Number of patches submitted ===
Martin Roth                  89 (49.444%)
Patrick Georgi               73 (40.556%)
Aaron Durbin                  9 (5.000%)
Stefan Reinauer               4 (2.222%)
Vladimir Serbinenko           3 (1.667%)
Werner Zeh                    1 (0.556%)
Nico Huber                    1 (0.556%)
Total Submitters: 7

coreboot changelog

The week leading up to November 15th has seen 132 commits (8bd1c36..3ca4116).
The leading themes were the removal of support for old mainboards, and the integration of more non-AGESA AMD support code for Family 10h to 15h that spans everything from fixes to memory configuration to workarounds to problems in the SATA controller, to new feature development, enabling CC6 power-state support and everything in-between.

Other chipset level contributions provided bug fixes to the drivers supporting Intel’s Skylake and AMD’s newer chipsets and mainboards (Kabini, Merlin Falcon, Mullins). Rockchip RK3288 now properly configures displays whether they’re connected through HDMI or DVI.

ARM/ARM64 saw some cleanup in its transition between stages to accommodate more processor configurations on ARM64 SoCs (that sometimes come with smaller 32bit cores for supporting purposes).

Also new is the Intel i8900 southbridge support that can be used with Sandy Bridge and Ivy Bridge, with an Intel reference board, the stargo2, and the SUNW Ultra40m2 board support.

The USB device mode driver for DesignWare’s USB2 controller (DWC2) in libpayload became more robust. The other notable field of work in libpayload is work with PDcurses’ upstream to synchronize their development and our copy.

In terms of the ongoing efforts to clean up old cruft across the entire tree, references to the getpir utility were dropped, after the tool was removed nearly two years ago. We also removed empty mainboard driver files that used to be required by the build system, even if the mainboard needed no special handling in its ramstage.
To help keep the quality bar high, automated testing now also covers intelvbttool. Another forward-looking addition is a clang-format specification of our coding style. It isn’t complete yet, but the hope is that we can eventually use it to simplify adhering to a consistent style and then enforce it.
The script to help organizing the commit log for release notes was pushed into util/release.

coreboot changelog

This changelog covers the week up to November 8th, spanning 63 commits (f6dc544..8bd1c36).

Last week’s code submissions gave us a lot of improvements pretty much everywhere, but the most user-visible change is probably the addition of ACPI S3 support to asrock/e350m1.

Speaking of ACPI, support for the DMAR tables used to report Intel IOMMU (VT-d) information to the operating system was significantly improved and is enabled on Sandy Bridge and Ivy Bridge.

Another user visible change is the rework of the fallback mechanism in our bootblock, making its CMOS-backed state handling more robust.

cbmem also saw some changes in that all its entries are now listed separately in cbtables (and util/cbmem uses that new structure) to cut down on what coreboot exposes as interface.

On the architectures side, ARM64 dropped its sec(urity) mon(itor) code in favor of using ARM Ltd’s Open Source arm-trusted-firmware, which we already import in 3rdparty.

The integration of commits to support AMD Fam15h CPUs with a non-AGESA implementation that integrates better with coreboot saw some progress. The AMD Binary PI side saw a number of bug fixes, too.

Boards based on Intel’s Skylake architecture also saw more development.

In addition to these targetted developments, there was also the usual set of bug fixes across the entire tree, providing some cleanups to the code and configuration system, some portability fixes for Windows and Mac OS X, deduplication of ACPI table generation on i945, and the removal of a Super IO that wasn’t used by any board (and thus isn’t even build tested).

The USB device mode driver in libpayload for the DesignWare USB2 controller works better under debugging, while the XHCI USB3 host controller driver gained a workaround for Intel XHCI controllers.

Finally, the board-status scripts that parse boot success reports into the list of supported motherboards on the wiki were modified to point out more clearly that the list on the wiki describes the current status. This became necessary because some users assumed that it’s outdated.
Since the i440bx mainboards that were at the top of the list may have contributed to that impression, desktop boards were moved down in favor of notebooks and server boards where most of the current development happens.

coreboot changelog

This changelog covers 2 weeks up to November 1st, during which coreboot-4.2 was released.
In that timeframe, the repository saw 214 commits spanning d98471c..f6dc544.

Before we get to the stuff that the tech media gets excited about, the first thing to report about is a bunch of efforts to improve the reliability of our tree and the automated testing we conduct.
abuild, the utility for automatically building the default configuration of every board in the tree, learned to deal with mainboard directories that cover multiple variants of a board. This brings back build test coverage for google/veyron.
Various programs in the util/ hierarchy of the tree are now automatically tested by our build test infrastructure, and the related code saw some refactoring to make testing more tools really simple. During that development, some Makefiles below util/ were also cleaned up.
Another area of clean ups was the conversion of `#ifdef` statements to using the `IS_ENABLED` macro. This ensures that even unused code paths are syntactically validated before the optimizer drops them, leading to the same binary output with better build test coverage.
In preparation of future improvements, we gained a lint tool for Kconfig files. It will be hooked up to the build system once the tree is clean, until then it provides a way to see what’s still missing. Check out `util/lint/kconfig_lint` if you’re curious.
As a proof of concept, util/fuzz-tests now provides an environment to test the jpeg decoder we ship for splash screens using afl-fuzz. The same approach can be applied to other coreboot components to find potential crash bugs (or worse).
Finally, several chip drivers were removed because they had no user in the tree anymore and thus saw no testing at all. Some of them will likely come back together with new mainboards that use them.
In addition to the code development to improve code quality, `util/scripts/maintainers.go` provides a way to query the MAINTAINERS database that we’re building, as one piece of a larger effort to improve code quality through formal submodule maintainership.
Another formal clean-up was the tree-wide removal of the last paragraph of the GPL license header in files, the one denoting where to obtain the license text. First, we ship it in the tree, second, it’s probably easier to get with a quick search engine request than by writing a letter to a US post address that may or may not be current.

Rockchip’s RK3288 gained support for additional power/clock states and a more robust EDID handling.
The ongoing effort to support booting in long mode (64 bit) on AMD64 progressed by the integration of changes to make SMM handling and AMD chipset drivers 64bit clean.
Some ACPI for older Intel chipsets was consolidated and is now used for multiple chipset generations.
The Intel GMA driver has also seen improvements, allowing brightness levels for laptop panels to be configured per board, and to disable the graphics chip entirely.
In terms of drivers, the aspeed driver provides native VGA text, and there were improvements to superio and i2c chip drivers, supporting more of their features.
Sandybridge now initializes CPUs serially for robustness reasons, and Intel FSP supports loading microcode from coreboot.

cbfstool now extracts stages and rmodules as ELF files, including relocation information for the former, so that roundtrips of add-stage/extract/add-stage become possible. It now also compiles more reliably on Cygwin.

libpayload saw the additional of a graphics library to layout images on a framebuffer using framebuffer independent coordinates, and some bug fixes to its USB drivers.

In addition to all those cleanups and little new features, coreboot also provides support for a couple new boards, in particular two Intel Skylake based boards by Google (google/chell and google/lars) as well as Asus KFSN4-DRE with K8 CPUs and Asus KGPE-D16 with more recent AMD CPUs (Fam10h and Fam15h).
All related chipsets also saw significant improvements, of which the still ongoing effort to provide non-AGESA implementations for the Fam15h CPU, as well as a ton (metric, in case you’re curious) of bugfixes and feature developments (for example Suspend to RAM) for all AMD CPUs starting with K8 is particularly notable.

Besides those changes, and minor (but valuable) contributions to improve the code style, there’s a bucket list of improvements across the entire tree: more robust SMM entry on i945, fixes to our SMBIOS table generation, changes to the resource allocator to become more robust and IOMMU friendly and to measure the time it takes, and improvements to the robustness of our build process.

Announcing coreboot 4.2

Halloween 2015 release – just as scary as that sounds
Dear coreboot community,

today marks the release of coreboot 4.2, the second release on our time based release schedule.
Since 4.1 there were 936 commits by 90 authors, increasing the code base by approximately 17000 lines of code. We saw 35 new contributors – welcome to coreboot! More than 34 developers were active as reviewers in that period.
Thanks go to all contributors who helped shape this release.

As with 4.1, the release tarballs are available at http://www.coreboot.org/releases/. There’s also a 4.2 tag and branch in the git repository.

This marks the first release that features a changelog comparing it to the previous release. There was some limited testing to make sure that the code is usable, and it boots on some devices. A structured test plan will only become part of the release procedure of future versions.
I’m grateful to Martin for assembling this release’s changelog.

This is also the first release that will be followed by the removal of old, unused code. There will be a policy on how to announce deprecation and removal of mainboard and chipset code for future releases.

Regards,
Patrick

Log of commit d5e6618a4f076610e683b174c4dd5108d960c785 to
commit 439a527014fa0cb3e4ef60ba59e5c57c737b4444

Changes between 4.1 and 4.2
—————————
Build system:
– Store a minimized coreboot config file in cbfs instead of the full config
– Store the payload config and revision in CBFS when that info is available
– Add -compression option for cbfs-files-y. Valid entries are now -file,
-type, -align, and -compression
– Change Microcode inclusion method from building .h files to pre-built binaries
– Update Builder tests for each commit to test utilities and run lint tools
– Many other small makefile and build changes and fixes
– Remove expert mode as a Kconfig option

Utilities:
– Many fixes and updates to many utilities (158 total commits)
– ifdtool: Update for skylake, handle region masks correctly
– crossgcc: Update to gcc 5.2.0
– kconfig: Add strict mode to fail on kconfig errors and warnings
– vgabios: Significant fixes to remove issues in linking into coreboot code
– Add script to parse MAINTAINERS file
– Add Kconfig lint tool
– Create a common library to share coreboot routines with utilities
– Significant changes and cleanup to cbfstool (81 commits). Major changes:
– Update cbfstool to change the internal location of FSP binaries when adding
them
– Decompress stage files on extraction and turn them into ELF binaries
– Header sizes are now variable, containing extended attributes
– Add compression tags to all cbfs headers so all cbfs files can be compressed
– Add and align CBFS components in one pass instead of two
– Add XIP support for X86 to relocate the romstage when it’s added
– Removed locate command as it’s no longer needed
– Add bootblock and cbfs_header file types so the master header knows about
them
– Prefer FMAP data to CBFS master header if FMAP data exists
– Add hashes to cbfs file metadata for verification of images

Payloads:
– SeaBIOS: update stable release from 1.7.5 to 1.8.2
– Libpayload had some significant changes (61 commits). Major changes:
– Add support for fmap tables
– Add support for SuperSpeed (3.0) USB hubs
– Updates and bugfixes for DesignWare OTG controller (DWC2)
– Add video_printf to print text with specified foreground & background
colors
– Updates to match changes to cbfs/cbfstool
– Add cbgfx, a library to show graphics and text on a display
– Read cbfs offset and size from sysinfo when available

Vendorcode:
– fsp_baytrail: Support Baytrail FSP Gold 4 release
– AMD binary PI: add support for fan control
– Work to get AMD AGESA to compile correctly as 64-bit code
– Add standalone (XIP) verstage support for x86 to verify romstage

Mainboards:
– New Mainboards:
– apple/macbookair4_2 – Sandy/Ivy Bridge with Panther / Cougar point
chipset
– asus/kgpe-d16 – AMD Family 10, SB700/SR5650 platform
– emulation/spike-riscv – RISCV virtualized platform
– google/chell – Intel Skylake chrome platform
– google/cyan – Intel Braswell chrome platform
– google/glados – Intel Skylake chrome platform
– google/lars – Intel Skylake chrome platform
– intel/kunimitsu – Intel Skylake chrome platform
– intel/sklrvp – Intel Skylake reference platform
– intel/strago – Intel Braswell chrome platform
– Cleanups of many mainboards – several patches each for:
– amd/bettong
– getac/p470
– google/auron, google/smaug and google/veyron_rialto
– pcengines/apu1
– siemens/mc_tcu3
– Combine the google/veyron_(jerry, mighty, minnie, pinkie, shark & speedy)
mainboards into the single google/veyron mainboard directory

Console:
– Add EM100 ‘hyper term’ spi console support in ramstage & smm
– Add console support for verstage

ARM:
– armv7: use asm coded memory operations for 32/16 bit read/write
– Many cleanups to the nvidia tegra chips (40 patches)

RISC-V:
– Add trap handling
– Add virtual Memory setup

X86:
– Remove and re-add Rangeley and Ivy Bridge / panther point FSP platforms
– Update microcode update parser to use stock AMD microcode blobs from CBFS
– ACPI: Align FACS to 64 byte boundary. Fixes FWTS error
– AMD/SB700: Init devices in early boot, restore power state after power
failure. Add IDE/SATA asl code
– Add initial support for AMD Socket G34 processors
– Add tick frequency to timestamp table to calculate boot times more accurately
– Unify X86 romstage / ramstage linking to match other platforms
– Start preparing X86 bootblock for non-memory-mapped BIOS media
– cpu/amd/car: Add Suspend to RAM (S3) support
– Native VGA init fixes on several platforms
– Significant updates to FSP 1.1 code for cleanup and cbfstool changes
– SMMhandler: on i945..nehalem, crash if LAPIC overlaps with ASEG to prevent
the memory sinkhole smm hack
Drivers:
– Add native text mode support for the Aspeed AST2050
– w83795: Add support for for fan control and voltage monitoring
– Intel GMA ACPI consolidation and improvements
– Set up the 8254 timer before running option ROMs
– Resource allocator: Page align memory mapped PCI resources

Lib:
– Derive fmap name from offset/size
– Several edid fixes
– Updates to cbfs matching changes in cbfstool

Submodules:
———–
3rdparty/blobs:
Total commits: 16
Log of commit 61d663e39bc96530900c3232ccea7365ab9dad0b to
commit aab093f0824b6d26b57a1ce220ba0d577e37ad49
– AMD Merlin Falcon: Update to CarrizoPI 1.1.0.0 (Binary PI 1.4)
– AMD Steppe Eagle: Update to MullinsPI 1.0.0.A (Binary PI 1.1)
– Update microcode to binary blobs. Remove old .h microcode files

3rdparty/arm-trusted-firmware:
– No Changes

3rdparty/vboot:
Total commits: 41
Log of commit fbf631c845c08299f0bcbae3f311c5807d34c0d6 to
commit d6723ed12b429834c2627c009aab58f0db20ce73
– Update the code to determine the write protect line gpio value
– Several updates to futility and image_signing scripts
– Update crossystem to accommodate Android mosys location
– Support reboot requested by secdata
– Add NV flag to default boot legacy OS

util/nvidia/cbootimage:
– No Changes

coreboot changelog

This report covers commits b66d673..d98471c, the week up to Sunday, 2015-10-18

This week has an interesting distribution in its commits: A few very large and impactful commits (and commit sets), but otherwise lots of tiny little things. The last months typically saw more cohesive changes each week, affecting a small number of subsystems or drivers – but not this week.

The biggest item in terms of code size was the reintroduction of Intel’s Rangeley SoC and related mainboard, which were found to still be requested by users after all.

The biggest item in terms of impact was probably the improvement of our automated build testing by adding our lint tests and build tests for various utilities to our build infrastructure, reporting any errors (and preventing them from creeping into the master branch). We don’t test all tools yet, but adding the others should be painless now. libpayload also gained a new test configuration so both libcurses implementations are now covered.

The vboot verstage concept was ported to x86 and added to FSP 1.1, allowing a separate verification stage to check romstage before executing it (from a potentially unsafe location).

AMD microcode can now be loaded from CBFS, and using their standard format instead of a custom layout that was used by coreboot until now.

Apart from these, changes happened all across the tree:
SMBIOS tables report memory vendors; ACPI was cleaned up to work better with new ACPI compiler versions; there’s better reporting for MTRR configurations, and related macros have more sensible names; the ARMv7 code avoids miscompilation with gcc-5.2, which is significant because that’s our standard compiler version; Intel GMA ACPI saw improvements; there were tons of style fixes in preparation to deal with the addition of lint tests to the automated tests; cbfstool can now add files after files of the same name were removed from an image; the coreinfo payload has the sense to reboot after it’s done; the cbmem utility is more robust, and several more cleanups and bugfixes.

coreboot changelog

This report covers commits b142b84afb to b66d673, up to Sunday, 2015-10-11
Last week saw the addition of the MacBookAir4,2 mainboard, which is especially notable because autoport did the largest part of the port – automatically, as the name implies.
In the course of this, autoport and some tools it relies on were improved.

Native VGA init saw some more bug fixes and better auto-configuration, so less values to configure by hand. Our other major reverse engineering effort, RAM init (and related functionality) for Sandy Bridge and Ivy Bridge, was also improved.

The ongoing vboot integration saw progress in adding support for a separate verification stage on x86 (not finished yet). In the course of these changes, the early x86 init code was refactored a bit to make moving Cache-as-RAM code to other stages easier. vboot also gained the first fixes to support CBFS as filesystem for the updateable flash regions, which still use a custom format.

There were also cleanups to the way the x86 bootblock is built, more closely matching our other stage build processes.

On the feature development side, Intel’s Skylake and Braswell chipsets as well as the related common Intel code saw numerous improvements and updates to new FSP interface versions.

The other notable feature was the addition of Dediprog EM100 “hyper term” support (ramstage only at this time) that allows using this SPI emulator as coreboot console output. Our em100 tool implementation also gained the ability to read this format.

libpayload gained the ability to deal with extended attributes containing hashes, which will be useful for payloads integrating with vboot.

Finally, Kconfig and the build system have seen a couple of cleanups, hiding items that aren’t user serviceable, as did buildgcc, our compiler toolchain generating script.