coreboot changelog

The week leading up to November 15th has seen 132 commits (8bd1c36..3ca4116).
The leading themes were the removal of support for old mainboards, and the integration of more non-AGESA AMD support code for Family 10h to 15h that spans everything from fixes to memory configuration to workarounds to problems in the SATA controller, to new feature development, enabling CC6 power-state support and everything in-between.

Other chipset level contributions provided bug fixes to the drivers supporting Intel’s Skylake and AMD’s newer chipsets and mainboards (Kabini, Merlin Falcon, Mullins). Rockchip RK3288 now properly configures displays whether they’re connected through HDMI or DVI.

ARM/ARM64 saw some cleanup in its transition between stages to accommodate more processor configurations on ARM64 SoCs (that sometimes come with smaller 32bit cores for supporting purposes).

Also new is the Intel i8900 southbridge support that can be used with Sandy Bridge and Ivy Bridge, with an Intel reference board, the stargo2, and the SUNW Ultra40m2 board support.

The USB device mode driver for DesignWare’s USB2 controller (DWC2) in libpayload became more robust. The other notable field of work in libpayload is work with PDcurses’ upstream to synchronize their development and our copy.

In terms of the ongoing efforts to clean up old cruft across the entire tree, references to the getpir utility were dropped, after the tool was removed nearly two years ago. We also removed empty mainboard driver files that used to be required by the build system, even if the mainboard needed no special handling in its ramstage.
To help keep the quality bar high, automated testing now also covers intelvbttool. Another forward-looking addition is a clang-format specification of our coding style. It isn’t complete yet, but the hope is that we can eventually use it to simplify adhering to a consistent style and then enforce it.
The script to help organizing the commit log for release notes was pushed into util/release.

coreboot changelog

This changelog covers the week up to November 8th, spanning 63 commits (f6dc544..8bd1c36).

Last week’s code submissions gave us a lot of improvements pretty much everywhere, but the most user-visible change is probably the addition of ACPI S3 support to asrock/e350m1.

Speaking of ACPI, support for the DMAR tables used to report Intel IOMMU (VT-d) information to the operating system was significantly improved and is enabled on Sandy Bridge and Ivy Bridge.

Another user visible change is the rework of the fallback mechanism in our bootblock, making its CMOS-backed state handling more robust.

cbmem also saw some changes in that all its entries are now listed separately in cbtables (and util/cbmem uses that new structure) to cut down on what coreboot exposes as interface.

On the architectures side, ARM64 dropped its sec(urity) mon(itor) code in favor of using ARM Ltd’s Open Source arm-trusted-firmware, which we already import in 3rdparty.

The integration of commits to support AMD Fam15h CPUs with a non-AGESA implementation that integrates better with coreboot saw some progress. The AMD Binary PI side saw a number of bug fixes, too.

Boards based on Intel’s Skylake architecture also saw more development.

In addition to these targetted developments, there was also the usual set of bug fixes across the entire tree, providing some cleanups to the code and configuration system, some portability fixes for Windows and Mac OS X, deduplication of ACPI table generation on i945, and the removal of a Super IO that wasn’t used by any board (and thus isn’t even build tested).

The USB device mode driver in libpayload for the DesignWare USB2 controller works better under debugging, while the XHCI USB3 host controller driver gained a workaround for Intel XHCI controllers.

Finally, the board-status scripts that parse boot success reports into the list of supported motherboards on the wiki were modified to point out more clearly that the list on the wiki describes the current status. This became necessary because some users assumed that it’s outdated.
Since the i440bx mainboards that were at the top of the list may have contributed to that impression, desktop boards were moved down in favor of notebooks and server boards where most of the current development happens.

coreboot changelog

This changelog covers 2 weeks up to November 1st, during which coreboot-4.2 was released.
In that timeframe, the repository saw 214 commits spanning d98471c..f6dc544.

Before we get to the stuff that the tech media gets excited about, the first thing to report about is a bunch of efforts to improve the reliability of our tree and the automated testing we conduct.
abuild, the utility for automatically building the default configuration of every board in the tree, learned to deal with mainboard directories that cover multiple variants of a board. This brings back build test coverage for google/veyron.
Various programs in the util/ hierarchy of the tree are now automatically tested by our build test infrastructure, and the related code saw some refactoring to make testing more tools really simple. During that development, some Makefiles below util/ were also cleaned up.
Another area of clean ups was the conversion of `#ifdef` statements to using the `IS_ENABLED` macro. This ensures that even unused code paths are syntactically validated before the optimizer drops them, leading to the same binary output with better build test coverage.
In preparation of future improvements, we gained a lint tool for Kconfig files. It will be hooked up to the build system once the tree is clean, until then it provides a way to see what’s still missing. Check out `util/lint/kconfig_lint` if you’re curious.
As a proof of concept, util/fuzz-tests now provides an environment to test the jpeg decoder we ship for splash screens using afl-fuzz. The same approach can be applied to other coreboot components to find potential crash bugs (or worse).
Finally, several chip drivers were removed because they had no user in the tree anymore and thus saw no testing at all. Some of them will likely come back together with new mainboards that use them.
In addition to the code development to improve code quality, `util/scripts/maintainers.go` provides a way to query the MAINTAINERS database that we’re building, as one piece of a larger effort to improve code quality through formal submodule maintainership.
Another formal clean-up was the tree-wide removal of the last paragraph of the GPL license header in files, the one denoting where to obtain the license text. First, we ship it in the tree, second, it’s probably easier to get with a quick search engine request than by writing a letter to a US post address that may or may not be current.

Rockchip’s RK3288 gained support for additional power/clock states and a more robust EDID handling.
The ongoing effort to support booting in long mode (64 bit) on AMD64 progressed by the integration of changes to make SMM handling and AMD chipset drivers 64bit clean.
Some ACPI for older Intel chipsets was consolidated and is now used for multiple chipset generations.
The Intel GMA driver has also seen improvements, allowing brightness levels for laptop panels to be configured per board, and to disable the graphics chip entirely.
In terms of drivers, the aspeed driver provides native VGA text, and there were improvements to superio and i2c chip drivers, supporting more of their features.
Sandybridge now initializes CPUs serially for robustness reasons, and Intel FSP supports loading microcode from coreboot.

cbfstool now extracts stages and rmodules as ELF files, including relocation information for the former, so that roundtrips of add-stage/extract/add-stage become possible. It now also compiles more reliably on Cygwin.

libpayload saw the additional of a graphics library to layout images on a framebuffer using framebuffer independent coordinates, and some bug fixes to its USB drivers.

In addition to all those cleanups and little new features, coreboot also provides support for a couple new boards, in particular two Intel Skylake based boards by Google (google/chell and google/lars) as well as Asus KFSN4-DRE with K8 CPUs and Asus KGPE-D16 with more recent AMD CPUs (Fam10h and Fam15h).
All related chipsets also saw significant improvements, of which the still ongoing effort to provide non-AGESA implementations for the Fam15h CPU, as well as a ton (metric, in case you’re curious) of bugfixes and feature developments (for example Suspend to RAM) for all AMD CPUs starting with K8 is particularly notable.

Besides those changes, and minor (but valuable) contributions to improve the code style, there’s a bucket list of improvements across the entire tree: more robust SMM entry on i945, fixes to our SMBIOS table generation, changes to the resource allocator to become more robust and IOMMU friendly and to measure the time it takes, and improvements to the robustness of our build process.

Announcing coreboot 4.2

Halloween 2015 release – just as scary as that sounds
Dear coreboot community,

today marks the release of coreboot 4.2, the second release on our time based release schedule.
Since 4.1 there were 936 commits by 90 authors, increasing the code base by approximately 17000 lines of code. We saw 35 new contributors – welcome to coreboot! More than 34 developers were active as reviewers in that period.
Thanks go to all contributors who helped shape this release.

As with 4.1, the release tarballs are available at There’s also a 4.2 tag and branch in the git repository.

This marks the first release that features a changelog comparing it to the previous release. There was some limited testing to make sure that the code is usable, and it boots on some devices. A structured test plan will only become part of the release procedure of future versions.
I’m grateful to Martin for assembling this release’s changelog.

This is also the first release that will be followed by the removal of old, unused code. There will be a policy on how to announce deprecation and removal of mainboard and chipset code for future releases.


Log of commit d5e6618a4f076610e683b174c4dd5108d960c785 to
commit 439a527014fa0cb3e4ef60ba59e5c57c737b4444

Changes between 4.1 and 4.2
Build system:
– Store a minimized coreboot config file in cbfs instead of the full config
– Store the payload config and revision in CBFS when that info is available
– Add -compression option for cbfs-files-y. Valid entries are now -file,
-type, -align, and -compression
– Change Microcode inclusion method from building .h files to pre-built binaries
– Update Builder tests for each commit to test utilities and run lint tools
– Many other small makefile and build changes and fixes
– Remove expert mode as a Kconfig option

– Many fixes and updates to many utilities (158 total commits)
– ifdtool: Update for skylake, handle region masks correctly
– crossgcc: Update to gcc 5.2.0
– kconfig: Add strict mode to fail on kconfig errors and warnings
– vgabios: Significant fixes to remove issues in linking into coreboot code
– Add script to parse MAINTAINERS file
– Add Kconfig lint tool
– Create a common library to share coreboot routines with utilities
– Significant changes and cleanup to cbfstool (81 commits). Major changes:
– Update cbfstool to change the internal location of FSP binaries when adding
– Decompress stage files on extraction and turn them into ELF binaries
– Header sizes are now variable, containing extended attributes
– Add compression tags to all cbfs headers so all cbfs files can be compressed
– Add and align CBFS components in one pass instead of two
– Add XIP support for X86 to relocate the romstage when it’s added
– Removed locate command as it’s no longer needed
– Add bootblock and cbfs_header file types so the master header knows about
– Prefer FMAP data to CBFS master header if FMAP data exists
– Add hashes to cbfs file metadata for verification of images

– SeaBIOS: update stable release from 1.7.5 to 1.8.2
– Libpayload had some significant changes (61 commits). Major changes:
– Add support for fmap tables
– Add support for SuperSpeed (3.0) USB hubs
– Updates and bugfixes for DesignWare OTG controller (DWC2)
– Add video_printf to print text with specified foreground & background
– Updates to match changes to cbfs/cbfstool
– Add cbgfx, a library to show graphics and text on a display
– Read cbfs offset and size from sysinfo when available

– fsp_baytrail: Support Baytrail FSP Gold 4 release
– AMD binary PI: add support for fan control
– Work to get AMD AGESA to compile correctly as 64-bit code
– Add standalone (XIP) verstage support for x86 to verify romstage

– New Mainboards:
– apple/macbookair4_2 – Sandy/Ivy Bridge with Panther / Cougar point
– asus/kgpe-d16 – AMD Family 10, SB700/SR5650 platform
– emulation/spike-riscv – RISCV virtualized platform
– google/chell – Intel Skylake chrome platform
– google/cyan – Intel Braswell chrome platform
– google/glados – Intel Skylake chrome platform
– google/lars – Intel Skylake chrome platform
– intel/kunimitsu – Intel Skylake chrome platform
– intel/sklrvp – Intel Skylake reference platform
– intel/strago – Intel Braswell chrome platform
– Cleanups of many mainboards – several patches each for:
– amd/bettong
– getac/p470
– google/auron, google/smaug and google/veyron_rialto
– pcengines/apu1
– siemens/mc_tcu3
– Combine the google/veyron_(jerry, mighty, minnie, pinkie, shark & speedy)
mainboards into the single google/veyron mainboard directory

– Add EM100 ‘hyper term’ spi console support in ramstage & smm
– Add console support for verstage

– armv7: use asm coded memory operations for 32/16 bit read/write
– Many cleanups to the nvidia tegra chips (40 patches)

– Add trap handling
– Add virtual Memory setup

– Remove and re-add Rangeley and Ivy Bridge / panther point FSP platforms
– Update microcode update parser to use stock AMD microcode blobs from CBFS
– ACPI: Align FACS to 64 byte boundary. Fixes FWTS error
– AMD/SB700: Init devices in early boot, restore power state after power
failure. Add IDE/SATA asl code
– Add initial support for AMD Socket G34 processors
– Add tick frequency to timestamp table to calculate boot times more accurately
– Unify X86 romstage / ramstage linking to match other platforms
– Start preparing X86 bootblock for non-memory-mapped BIOS media
– cpu/amd/car: Add Suspend to RAM (S3) support
– Native VGA init fixes on several platforms
– Significant updates to FSP 1.1 code for cleanup and cbfstool changes
– SMMhandler: on i945..nehalem, crash if LAPIC overlaps with ASEG to prevent
the memory sinkhole smm hack
– Add native text mode support for the Aspeed AST2050
– w83795: Add support for for fan control and voltage monitoring
– Intel GMA ACPI consolidation and improvements
– Set up the 8254 timer before running option ROMs
– Resource allocator: Page align memory mapped PCI resources

– Derive fmap name from offset/size
– Several edid fixes
– Updates to cbfs matching changes in cbfstool

Total commits: 16
Log of commit 61d663e39bc96530900c3232ccea7365ab9dad0b to
commit aab093f0824b6d26b57a1ce220ba0d577e37ad49
– AMD Merlin Falcon: Update to CarrizoPI (Binary PI 1.4)
– AMD Steppe Eagle: Update to MullinsPI 1.0.0.A (Binary PI 1.1)
– Update microcode to binary blobs. Remove old .h microcode files

– No Changes

Total commits: 41
Log of commit fbf631c845c08299f0bcbae3f311c5807d34c0d6 to
commit d6723ed12b429834c2627c009aab58f0db20ce73
– Update the code to determine the write protect line gpio value
– Several updates to futility and image_signing scripts
– Update crossystem to accommodate Android mosys location
– Support reboot requested by secdata
– Add NV flag to default boot legacy OS

– No Changes

coreboot changelog

This report covers commits b66d673..d98471c, the week up to Sunday, 2015-10-18

This week has an interesting distribution in its commits: A few very large and impactful commits (and commit sets), but otherwise lots of tiny little things. The last months typically saw more cohesive changes each week, affecting a small number of subsystems or drivers – but not this week.

The biggest item in terms of code size was the reintroduction of Intel’s Rangeley SoC and related mainboard, which were found to still be requested by users after all.

The biggest item in terms of impact was probably the improvement of our automated build testing by adding our lint tests and build tests for various utilities to our build infrastructure, reporting any errors (and preventing them from creeping into the master branch). We don’t test all tools yet, but adding the others should be painless now. libpayload also gained a new test configuration so both libcurses implementations are now covered.

The vboot verstage concept was ported to x86 and added to FSP 1.1, allowing a separate verification stage to check romstage before executing it (from a potentially unsafe location).

AMD microcode can now be loaded from CBFS, and using their standard format instead of a custom layout that was used by coreboot until now.

Apart from these, changes happened all across the tree:
SMBIOS tables report memory vendors; ACPI was cleaned up to work better with new ACPI compiler versions; there’s better reporting for MTRR configurations, and related macros have more sensible names; the ARMv7 code avoids miscompilation with gcc-5.2, which is significant because that’s our standard compiler version; Intel GMA ACPI saw improvements; there were tons of style fixes in preparation to deal with the addition of lint tests to the automated tests; cbfstool can now add files after files of the same name were removed from an image; the coreinfo payload has the sense to reboot after it’s done; the cbmem utility is more robust, and several more cleanups and bugfixes.

coreboot changelog

This report covers commits b142b84afb to b66d673, up to Sunday, 2015-10-11
Last week saw the addition of the MacBookAir4,2 mainboard, which is especially notable because autoport did the largest part of the port – automatically, as the name implies.
In the course of this, autoport and some tools it relies on were improved.

Native VGA init saw some more bug fixes and better auto-configuration, so less values to configure by hand. Our other major reverse engineering effort, RAM init (and related functionality) for Sandy Bridge and Ivy Bridge, was also improved.

The ongoing vboot integration saw progress in adding support for a separate verification stage on x86 (not finished yet). In the course of these changes, the early x86 init code was refactored a bit to make moving Cache-as-RAM code to other stages easier. vboot also gained the first fixes to support CBFS as filesystem for the updateable flash regions, which still use a custom format.

There were also cleanups to the way the x86 bootblock is built, more closely matching our other stage build processes.

On the feature development side, Intel’s Skylake and Braswell chipsets as well as the related common Intel code saw numerous improvements and updates to new FSP interface versions.

The other notable feature was the addition of Dediprog EM100 “hyper term” support (ramstage only at this time) that allows using this SPI emulator as coreboot console output. Our em100 tool implementation also gained the ability to read this format.

libpayload gained the ability to deal with extended attributes containing hashes, which will be useful for payloads integrating with vboot.

Finally, Kconfig and the build system have seen a couple of cleanups, hiding items that aren’t user serviceable, as did buildgcc, our compiler toolchain generating script.

coreboot changelog

This report covers commits 2f953d3 to b142b84afb, up to early Monday, 2015-10-05

Last week has seen the removal of FSP support for Sandybridge and Ivy Bridge, in favor of the native raminit code and the originally supported MRC binary, with the native code path becoming the default code path on these chipsets.

The microcode handling was reworked further so that Intel microcode is now stored as binary files in 3rdparty/blobs, instead of being kept in the coreboot tree and processed by the compiler.

Development on cbfstool continued, adding the capability to relocate FSP binaries on add, and the capability to store hashes of file data to the file header, which can be a useful primitive for a verified boot process.
For this, the recently introduced commonlib was used to share code between coreboot and cbfstool.

The verstage code for Chrome OS’ vboot was refactored to allow this separate verification stage on x86. verstage was introduced to allow moving the romstage to updateable storage (that can be used only after verification which is what verstage is doing), and the idea is to make this also available on x86.
The change allowed code deduplication for several ARM chipsets, too.
For this, our Cache-as-RAM initialization code also became more independent from romstage code.

Kconfig’s strict mode (akin to gcc’s “warnings-as-errors”) is now available in more of its frontends. This should help fix Kconfig issues.

Several bug fixes also made it in, improving support for older gcc versions, for building on Mac OS X, to get native VGA init to build again for multiple Intel chipsets and more.

coreboot changelog, most-of-september edition

This report covers 410f9ad to 2f953d304e

The biweekly cadence messed up my timing so this report covers five weeks and for that reason gets to report more development (314 commits).

The biggest chunk (over one third of the commits) covers Intel Skylake development, where boards and chipset code saw misc improvements and tons of clean ups (eg. dropping ACPI code and fragments in the devicetrees that were inherited from older chipset development and aren’t appropriate anymore).
There also was a notable effort of unifying common code across the more recent Intel SoCs, removing lots of duplicated code all over the place.

As far as cleaning up the code base goes, we also got rid of a number of Kconfig definitions and uses across the tree (Intel, AMD, MIPS – something for everybody). Some definitions were booleans that were always enabled with no reason to ever disable, other symbols were selected even though they didn’t even exist anymore.

Another field of clean-up work was the EDID code used for native graphics init, which is the default on ARM SoCs (simply because there is nothing like VGABIOS there). Two structs that both defined standard fields of this “Extended Display Identification Data” standard were reworked to avoid the duplication, avoiding issues where a field is filled in for one representation but not the other.

On x86, the romstage is now relocated for its final location in CBFS by cbfstool, obsoleting the old approach that had us link it twice, once to determine its final size and then to the actual location it’s supposed to run from. This reused code from our rmodule support that already contained knowledge about relocation fields.
In the future this same approach may be extended to other files that need to be executed in place such as the FSP binary.
This effort also had x86’s linking setup become more similar to what all other architectures are doing, for romstage and ramstage, as well as some more clean-ups in the general area.
Finally, the way the romstage is linked together was simplified, resulting in less “magic” in the build system to collect the various pieces of initialization code.

The romstage change eliminated the need for cbfstool’s “locate” command, and so it was removed. cbfstool also saw other extensions, the biggest one a compatible change to the format to allow for per-file attributes in CBFS. These attributes can contain additional information about a file, currently the compression method and uncompressed size of a file. cbfstool and the build system were extended to allow compressing files, libpayload is able to uncompress these files.
The libpayload change leads to a change in behavior for some specialized cbfs access routines (eg. cbfs_load_optionrom) in that they return malloc’d memory instead of a pointer into CBFS, which may lead to a memory leak in payloads.
cbfstool’s support for flashmap “partition tables” was also improved: It already could create flashmap partitioned images, and now can create a backward compatible CBFS master header, so an fmap-based image can still be used by older CBFS parsers (which right now means: pretty much all of them).
If an fmap is available, cbfstool will prefer it over a master header, but that should have no visible effect yet.
The changes also seeked to improve the internal structure of the cbfstool codebase, although much more work is necessary in that area.

libpayload saw the addition of a video_printf function to write colored text with support for text justification.
Its USB device controller driver for DeviceWare based controllers became more robust, too.
It also got back a POSIX-compatible ffs() implementation that was dropped for a while, got coreboot-compatible write8/16/32 implementations and saw a couple of bugfixes.

Another clean-up topic is the reduction of code that is #ifdef’d away for invidivual stages. To this end, we now expose declarations (but no definitions) for various functions even in romstage, so files compile. Use of ramstage-level functions like malloc in romstage still fail, but at link time. The linker is smart enough these days to pinpoint the error to a line in a source file, so no information is lost. The upside is that the code flow isn’t broken by preprocessor conditionals every few lines.
In a similar light, more #if CONFIG_FOO statements were replaced by if (IS_ENABLED(CONFIG_FOO)), exposing the guarded code to the compiler, which avoids errors from accumulating in non-standard configurations: Now the code needs to pass the compiler at least syntactically even in a standard configuration.
Finally, Chrome OS vboot related code was abstracted away in SoC code, to make it more useful in non-Chrome OS configurations more easily.

To reduce code duplication, we also started building a common library (src/commonlib/), containing things like CBFS data structure declarations or endianess handling functions that are useful in both coreboot and its utilities.

On the AMD side, there were various bugfixes both for new (merlin falcon) and old (Fam10) chipsets.

ARM64 and Tegra210 saw various bugfixes and improvements to power use. For the latter, coreboot also learned how to reserve memory for other functions than the main processor.
Rockchip’s RK3288 ARMv7 SoC also saw a number of bug fixes and the code was restructured to use a single mainboard directory for a large number of very similar Google Veyron mainboards based on that SoC.

Our RISCV support now boots on the Spike simulator which (besides supporting a wider variety of emulators) is notable because unlike the QEmu RISCV support, Spike supports RISCV’s revised ABI.
Speaking of emulators, recent versions of qemu-x86 expect the firmware to initialize the LAPIC, which we now do.

The timestamps recording code was extended to also store the timebase (ticks) so that the userspace tool in the OS doesn’t need to try to figure it out – probably wrongly because by the time the OS started, the clock changed and with it, on some CPUs, the tick duration.
cbmem also gained an option “-T” to display timestamps in a machine readable format.
During the course of that development, some timestamps code was simplified, relying more on generic code over per-chipset implementations.

The ongoing effort to move CPU microcode into CBFS (and to store these as binaries in 3rdparty/blobs instead of header files in the main sources) saw some progress.

Our crosscompiler generator script is more helpful on errors and learned building gcc (the “GNU compiler suite”) for non-C languages, including some extensions to support Ada in particular.
abuild now produces proper logs when building the tools (below util/), making it easier to track down issues in that area from error reports on our continuous build system.

The standard seabios released used by our build system is now 1.8.2, up from 1.7.5. In other payload related news, coreboot doesn’t initialize PS/2 keyboards by itself by default, but expects the payload to do so. The option to re-enable the initialization (as well as the code it controls) is still around.

The intel-related utilities saw some improvements, with ifdtool supporting the new IFD v2 better (as used on Skylake), and inteltool able to detect Intel’s 4-Series.

The tree also saw some improvements with regard to portability and should behave better when building on MinGW, Cygwin, Mac OS X and FreeBSD host.

coreboot changelog – Weeks of 2015-08-10 and 2015-08-17

this report covers commits 1cbef1c to 410f9ad

The vast majority of changes in these two weeks were upstreamed from Chrome OS and cover work on the Intel Skylake chipset and two mainboards based on it.

QEmu and Getac P470 saw a couple of improvements.
On AMD, there were some bugfixes to Fam10h concerning VGA memory and SMM initialization. The latter was in response to the Memory Sinkhole vulnerability, although it is as yet unclear if it even affects AMD.
Finally, an important memory structure used on pre-AGESA AMD code is now also usable outside Cache-as-RAM.
There was more progress on fixing 64bit issues across the codebase.

Our reference compiler was updated to gcc 5.2. This became necessary to support an update to the RISC-V specification.

Our other tools also saw a couple of improvements: ifdtool now works for descriptors on Skylake and newer platforms. cbfstool saw some refactorings that allow us to extend the format. cbmem now emits the accumulated boot time.

In our configuration system, the Kconfig definitions were cleaned up, so that boards don’t define symbols that their code never uses, that Chrome OS capable boards define “MAINBOARD_HAS_CHROMEOS” (which defines the capability) instead of “CHROMEOS” (which defines that this mode should be
used) and that dependencies between Kconfig options become more consistent.
There is a pending commit on gerrit to enforce clean dependencies by making errors out of kconfig’s warnings, that the latter changes prepare for.

On the build system side, it is now possible to build SeaBIOS as part of our build system even with an enabled ccache. The payload config and revision can also be stored in CBFS for better reproducibility. Finally, it’s possible to override the location from where the vboot source code for Chrome OS-style verified boot is taken from.

In libpayload, the non-accelerated memmove implementation now also works with size == 0 (instead of trying to move 4GB), and there were a couple of bug fixes to the DWC2 (some ARM) and XHCI (USB3) controller drivers, including support for the newer XHCI 1.1 specification.

coreboot changelog – Weeks of 2015-07-27 and 2015-08-03

This covers commits ef0158ec up to commit 1cbef1c
Development is typically slower during the summer and 2015 is no exception, so the report switches to a biweekly installment for a while.

The last two weeks have seen improvements in our development tools:
coreboot upstream can now build Chrome OS boards with Chrome OS features (verified boot, interaction with Chrome EC, flash based error logging) enabled, and the projects builders at are now routinely building these configurations alongside the regular default configs for all boards.
The builders now run ‘make what-jenkins does’ (see coreboot/ instead of a hard-coded set of commands, which provides the community the capability to adapt the test build without admin intervention.
When adding the .config used for building an image into said image, it’s now minimized which gives visibility to the relevant changes to the config compared to the board’s defaults.
Kconfig features a strict mode, which acts as a ‘warnings-as-errors’ equivalent and fails the build if kconfig would emit any warning. Since we still have a couple of those in the tree, it’s not enabled yet.
For users of cscope or ctags, we now have new make targets to create tree-wide indexes (make ctags-project cscope-project).

Reproducible builds got a boost by fixes to the build.h generator script, which can finally emit stable timestamps based on the git revision, instead of the local time.

External payload integration was coalesced within payloads/external, with more work in progress. The integrated SeaBIOS build can now also be used when building with ccache. libpayload gained robustness in different developer environments, being smarter about looking for compilers, configs and include files in all the right places.

On the Free Software side, more microcode blobs were moved to the 3rdparty/blobs repository and one false positive that libreboot’s blob detector tripped over was eliminated, and with a little more progress, it should soon be possible to build from a fully blob-free coreboot tree. Before you get your hopes up, please note that the result may not be very useful on a lot of boards, so more care must be taken.

The effort to make coreboot capable of booting in 64bit mode on x86-64 is still ongoing and saw the integration of more commits.

coreboot should have an easier time again when building on Cygwin and BSD systems.

Skylake was the chipset with the largest amount of work in the 2 weeks, but there was also the addition of a coreboot port for RISC-V’s Spike ISA Simulator, contributions to the AMD Bettong mainboard and its chipset drivers, as well as fixes and cleanups to AMD K8 and Intel i945.

In terms of style, a bunch of extraneous whitespaces, indenting errors and FSF addresses were also dealt with.