Author: Felix Singer

coreboot 24.02 and 24.02.1 released!

The coreboot project is happy to announce our release for February 2024. Over the past three months, our contributors have focused on refining the coreboot codebase, generally prioritizing cleanup and quality enhancements. We extend our gratitude to all the contributors who have dedicated their time and expertise. Thank you for your invaluable contributions to this vital phase of maintenance and optimization.

The next release is scheduled for mid-May.

Release number format update

The previous release was the last to use the incrementing 4.xx release name scheme. For this and future releases, coreboot has switched to a Year.Month.Sub-version naming scheme. As such, the next release, scheduled for May of 2024 will be numbered 24.05, with the sub-version of 00 implied. If we need to do a fix or incremental release, we’ll append the values .01, .02 and so on to the initial release value.

The master branch is being deleted

The coreboot project changed from master to main roughly 6 months ago, and has been keeping the two branches in sync since then to ease the transition. As of this release, we are getting rid of the master branch completely. Please make sure any scripts you’re using that reference the ‘master’ branch have been switched to ‘main’.

Release 24.02.1

lib/rtc: Fix off-by-one error in February day count in leap year

The month argument passed to rtc\_month\_days is 0-based, not 1-based. This results in the RTC being reverted to the build date constantly on 29th February 2024.

Significant or interesting changes

acpi: Add Arm IO Remapping Table structures

Input Output Remapping Table (IORT) represents the IO topology of an Arm based system.

Document number: ARM DEN 0049E.e, Sep 2022

acpi: Add PPTT support

This patch adds code to generate Processor Properties Topology Tables (PPTT) compliant to the ACPI 6.4 specification.

  • The ‘acpi_get_pptt_topology’ hook is mandatory once ACPI_PPTT is selected. Its purpose is to return a pointer to a topology tree, which describes the relationship between CPUs and caches. The hook can be provided by, for example, mainboard code.

Background: We are currently working on mainboard code for qemu-sbsa and Neoverse N2. Both require a valid PPTT table. Patch was tested against the qemu-sbsa board.

acpi: Add support for WDAT table

This commit lays the groundwork for implementing the ACPI WDAT (Watchdog Action Table) table specification. The WDAT is a special ACPI table introduced by Microsoft that describes the watchdog for the OS.

Platforms that need to implement the WDAT table must describe the hardware watchdog management operations as described in the specification. See “Links to ACPI-Related Documents” (http://uefi.org/acpi) under the heading “Watchdog Action Table”.

lib/jpeg: Replace decoder with Wuffs’ implementation

To quote its repo[0]: Wuffs is a memory-safe programming language (and a standard library written in that language) for Wrangling Untrusted File Formats Safely. Wrangling includes parsing, decoding and encoding.

It compiles its library, written in its own language, to a C/C++ source file that can then be used independently without needing support for the language. That library is now imported to src/vendorcode/wuffs/.

This change modifies our linters to ignore that directory because it’s supposed to contain the wuffs compiler’s result verbatim.

Nigel Tao provided an initial wrapper around wuffs’ jpeg decoder that implements our JPEG API. I further changed it a bit regarding data placement, dropped stuff from our API that wasn’t ever used, or isn’t used anymore, and generally made it fit coreboot a bit better. Features are Nigel’s, bugs are mine.

This commit also adapts our jpeg fuzz test to work with the modified API. After limiting it to deal only with approximately screen sized inputs, it fuzzed for 25 hours CPU time without a single hang or crash. This is a notable improvement over running the test with our old decoder which crashes within a minute.

Finally, I tried the new parser with a pretty-much-random JPEG file I got from the internet, and it just showed it (once the resolution matched), which is also a notable improvement over the old decoder which is very particular about the subset of JPEG it supports.

In terms of code size, a QEmu build’s ramstage increases from 128060 bytes decompressed (64121 bytes after LZMA) to 172304 bytes decompressed (82734 bytes after LZMA).

[0] https://github.com/google/wuffs

Additional coreboot changes

  • Rename Makefiles from .inc to .mk to better identify them
  • SPI: Add GD25LQ255E and IS25WP256D chip support
  • device: Add support for multiple PCI segment groups
  • device: Drop unused multiple downstream link support
  • device: Rename bus and link_list to upstream and downstream
  • Updated devicetree files for modern Intel platforms to use chipset.cb
  • Updated xeon-sp to use the coreboot allocator

Changes to external resources

Toolchain updates

  • Add buildgcc support for Apple M1/M2 devices
  • Upgrade GCC from 11.4.0 to 13.2.0
  • Update CMake from 3.26.4 to 3.27.7
  • Uprev to Kconfig from Linux 6.7

Git submodule pointers

  • 3rdparty/amd_blobs: Update from commit id e4519efca7 to 64cdd7c8ef (5 commits)
  • 3rdparty/arm-trusted-firmware: Update from commit id 88b2d81345 to 17bef2248d (701 commits)
  • 3rdparty/fsp: Update from commit id 481ea7cf0b to 507ef01cce (16 commits)
  • 3rdparty/intel-microcode: Update from commit id 6788bb07eb to ece0d294a2 (1 commit)
  • 3rdparty/vboot: Update from commit id 24cb127a5e to 3d37d2aafe (121 commits)

External payloads

  • payload/grub2: Update from 2.06 to 2.12
  • payload/seabios: Update from 1.16.2 to 1.16.3

Platform Updates

Added mainboards

  • Google: Dita
  • Google: Xol
  • Lenovo: ThinkPad X230 eDP Mod (2K/FHD)

Removed mainboards

  • Google -> Primus4ES

Statistics from the 4.22 to the 24.02 release

  • Total Commits: 815
  • Average Commits per day: 8.63
  • Total lines added: 105433
  • Average lines added per commit: 129.37
  • Number of patches adding more than 100 lines: 47
  • Average lines added per small commit: 41.34
  • Total lines removed: 16534
  • Average lines removed per commit: 20.29
  • Total difference between added and removed: 88899
  • Total authors: 111
  • New authors: 19

Significant Known and Open Issues

  • AMD chromebooks will not work with the signed PSP_verstage images and the version of verstage used in coreboot 24.02.

Issues from the coreboot bugtracker: ticket.coreboot.org

coreboot-wide or architecture-wide issues

#Subject
522 ‘region_overlap()’ issues due to an integer overflow.
519make gconfig – could not find glade file
518make xconfig – g++: fatal error: no input files

Payload-specific issues

#Subject
499edk2 boot fails with RESOURCE_ALLOCATION_TOP_DOWN enabled
496Missing malloc check in libpayload
484No USB keyboard support with secondary payloads
414X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT

Platform-specific issues

#Subject
517lenovo x230 boot stuck with connected external monitor
509SD Card hotplug not working on Apollo Lake
507Windows GPU driver fails on Google guybrush & skyrim boards
506APL/GML don’t boot OS when CPU microcode included “from tree”
505Harcuvar CRB – 15 of 16 cores present in the operating system
499T440p – EDK2 fails with RESOURCE_ALLOCATION_TOP_DOWN enabled
495Stoney Chromebooks not booting PSPSecureOS
478X200 booting Linux takes a long time with TSC
474X200s crashes after graphic init with 8GB RAM
457Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb
453Intel HDMI / DP Audio not present in Windows after libgfxinit
449ThinkPad T440p fail to start, continuous beeping & LED blinking
448Thinkpad T440P ACPI Battery Value Issues
446Optiplex 9010 No Post
439Lenovo X201 Turbo Boost not working (stuck on 2,4GHz)
427x200: Two battery charging issues
412x230 reboots on suspend
393T500 restarts rather than waking up from suspend
350I225 PCIe device not detected on Harcuvar

coreboot Links and Contact Information

coreboot 4.22 & 4.22.01 have been released

The next release is planned for the 19th of February, 2024

These notes cover the latest updates and improvements to coreboot over the past three months. A big thank you to the returning contributors as well as the 14 individuals who committed code for the first time. We greatly appreciate everyone’s dedication and expertise. As with past releases, this one reflects a commitment to open source innovation, security enhancements, and expanding hardware support.

4.22.01 release

The week between tagging a release and announcing it publicly is used to test the tagged version and make sure everything is working as we expect. This is done instead of freezing the tree and doing release candidates before the release.

For the 4.22 release cycle we found an uninitialized variable error on the sandybridge/ivybridge platforms and rolled that into the 4.22.01 release package.

coreboot version naming update

This release is the last release to use the incrementing 4.xx release name scheme. For future releases, coreboot is switching to a Year.Month.Sub-version naming scheme. As such, the next release, scheduled for February of 2024 will be numbered 24.02, with the sub-version of 00 implied. If we need to do a fix or future release of the 24.02 release, we’ll append the values .01, .02 and so on to the initial release value.

coreboot default branch update

Immediately after the 4.21 release, the coreboot project changed the default git branch from ‘master’ to ‘main’. For the first couple of months after the change, The master branch was synced with the main branch several times a day, allowing people time to update any scripts. As of 2023-11-01, the sync rate has slowed to once a week. This will continue until the next release, at which time the master branch will be removed.

Significant or interesting changes

x86: support .data section for pre-memory stages

x86 pre-memory stages did not support the .data section and as a result developers were required to include runtime initialization code instead of relying on C global variable definitions.

Other platforms do not have that limitation. Hence, resolving it helps to align code and reduce compilation-based restrictions (cf. the use of ENV_HAS_DATA_SECTION compilation flag in various places of coreboot code).

There were three types of binary to consider:

  1. eXecute-In-Place pre-memory stages
  2. bootblock stage is a bit different as it uses Cache-As-Ram but the memory mapping and its entry code different
  3. pre-memory stages loaded in and executed from Cache-As-RAM (cf. CONFIG_NO_XIP_EARLY_STAGES).

eXecute-In-Place pre-memory stages (#1) rely on a new ELF segment as the code segment Virtual Memory Address and Load Memory Address are identical but the data needs to be linked in cache-As-RAM (VMA) to be stored right after the code (LMA).

bootblock (#2) also uses this new segment to store the data right after the code and it loads it to Cache-As-RAM at runtime. However, the code involved is different.

Not eXecute-In-Place pre-memory stages (#3) did not need any special work other than enabling a .data section as the code and data VMA / LMA translation vector is the same.

Related important commits:

  • c9cae530e5 (“cbfstool: Make add-stage support multiple ignore sections”)
  • 79f2e1fc8b (“cbfstool: Make add-stage support multiple loadable segments”)
  • b7832de026 (“x86: Add .data section support for pre-memory stages”)

x86: Support CBFS cache for pre-memory stages and ramstage

The CBFS cache scratchpad offers a generic way to decompress CBFS files through the cbfs_map() function without having to reserve a per-file specific memory region.

CBFS cache x86 support has been added to pre-memory stages and ramstage.

  1. pre-memory stages: The new PRERAM_CBFS_CACHE_SIZE Kconfig can be used to set the pre-memory stages CBFS cache size. A cache size of zero disables the CBFS cache feature for all pre-memory stages. The default value is 16 KiB which seems a reasonable minimal value enough to satisfy basic needs such as the decompression of a small configuration file. This setting can be adjusted depending on the platform’s needs and capabilities. Note that we have set this size to zero for all the platforms without enough space in Cache-As-RAM to accommodate the default size.
  2. ramstage: The new RAMSTAGE_CBFS_CACHE_SIZE Kconfig can be used to set the ramstage CBFS cache size. A cache size of zero disables the CBFS cache feature for ramstage. Similarly to pre-memory stages support, the default size is 16 KiB. As we want to support the S3 suspend/resume use case, the CBFS cache memory cannot be released to the operating system and therefore cannot be an unreserved memory region. The ramstage CBFS cache scratchpad is defined as a simple C static buffer as it allows us to keep the simple and robust design of the static initialization of the cbfs_cache global variable (cf. src/lib/cbfs.c). However, since some AMD SoCs (cf. SOC_AMD_COMMON_BLOCK_NONCAR Kconfig) already define a _cbfs_cache region we also introduced a POSTRAM_CBFS_CACHE_IN_BSS Kconfig to gate the use of a static buffer as the CBFS cache scratchpad.

Allow romstage to be combined into the bootblock

Having a separate romstage is only desirable:

  • with advanced setups like vboot or normal/fallback
  • boot medium is slow at startup (some ARM SOCs)
  • bootblock is limited in size (Intel APL 32K)

When this is not the case there is no need for the extra complexity that romstage brings. Including the romstage sources inside the bootblock substantially reduces the total code footprint. Often the resulting code is 10-20k smaller.

This is controlled via a Kconfig option.

soc/intel/cmn/gfx: Add API to report presence of external display

This implements an API to report the presence of an external display on Intel silicon. The API uses information from the transcoder and framebuffer to determine if an external display is connected.

For example, if the transcoder is attached to any DDI ports other than DDI-A (eDP), and the framebuffer is initialized, then it is likely that an external display is present.

This information can be used by payloads to determine whether or not to power on the display, even if eDP is not initialized.

device/pci_rom: Set VBIOS checksum when filling VFCT table

AMD’s Windows display drivers validate the checksum of the VBIOS data in the VFCT table (which gets modified by the FSP GOP driver), so ensure it is set correctly after copying the VBIOS into the table if the FSP GOP driver was run. Without the correct checksum, the Windows GPU drivers will fail to load with a code 43 error in Device Manager.

Additional coreboot changes

  • Move all ‘select’ statements from Kconfig.name files to Kconfig
  • acpigen now generates variable-length PkgLength fields instead of a fixed 3-byte size to improve compatibility and to bring it in line with IASL
  • Work to allow Windows to run on more Chromebooks
  • General cleanup and reformatting
  • Add initial AMD openSIL implementation
  • Add ACPI table generation for ARM64
  • Stop resetting CMOS during s3 resume even if marked as invalid
  • Comply with ACPI specification by making _STR Unicode strings
  • Fix SMM get_save_state calculation, which was broken when STM was enabled
  • SNB+MRC boards: Migrate MRC settings to devicetree
  • Work on chipset devicetrees for all platforms

Changes to external resources

Toolchain updates

  • Upgrade GMP from 6.2.1 to 6.3.0
  • Upgrade binutils from 2.40 to 2.41
  • Upgrade MPFR from 4.2.0 to 4.2.1

Git submodule pointers

  • amd_blobs: Update from commit id 6a1e1457af to e4519efca7 (16 commits)
  • arm-trusted-firmware: Update from commit id 37366af8d4 to 88b2d81345 (214 commits)
  • fsp: Update from commit id 3beceb01f9 to 481ea7cf0b (15 commits)
  • intel-microcode: Update from commit id 6f36ebde45 to 6788bb07eb (1 commit)
  • vboot: Update from commit id 0c11187c75 to 24cb127a5e (24 commits)
  • genoa_poc/opensil: New submodule updated to 0411c75e17 (41 commits)

External payloads

  • U-Boot: Use github mirror and the latest version
  • edk2: Update default branch for MrChromebox repo to 2023-09

Platform Updates

Added 17 mainboards

  • AMD Onyx
  • Google: Anraggar
  • Google: Brox
  • Google: Chinchou
  • Google: Ciri
  • Google: Deku
  • Google: Deku4ES
  • Google: Dexi
  • Google: Dochi
  • Google: Nokris
  • Google: Quandiso
  • Google: Rex4ES EC ISH
  • Intel: Meteorlake-P RVP with Chrome EC for non-Prod Silicon
  • Purism Librem 11
  • Purism Librem L1UM v2
  • Siemens FA EHL
  • Supermicro X11SSW-F

Added 1 SoC

  • src/soc/amd/genoa

Statistics from the 4.21 to the 4.22 release

  • Total Commits: 977
  • Average Commits per day: 10.98
  • Total lines added: 62993
  • Average lines added per commit: 64.48
  • Number of patches adding more than 100 lines: 60
  • Average lines added per small commit: 37.55
  • Total lines removed: 30042
  • Average lines removed per commit: 30.75
  • Total difference between added and removed: 32951
  • Total authors: 135
  • New authors: 14

Significant Known and Open Issues

Issues from the coreboot bugtracker: https://ticket.coreboot.org/

Payload-specific issues

Bug #Subject
499edk2 boot fails with RESOURCE_ALLOCATION_TOP_DOWN enabled
496Missing malloc check in libpayload
484No USB keyboard support with secondary payloads
414X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT

Platform-specific issues

Bug #Subject
509SD Card hotplug not working on Apollo Lake
507Windows GPU driver fails on Google guybrush & skyrim boards
506APL/GML don’t boot OS when CPU microcode included “from tree”
505Harcuvar CRB – 15 of 16 cores present in the operating system
499T440p – EDK2 fails with RESOURCE_ALLOCATION_TOP_DOWN enabled
495Stoney Chromebooks not booting PSPSecureOS
478X200 booting Linux takes a long time with TSC
474X200s crashes after graphic init with 8GB RAM
457Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb
453Intel HDMI / DP Audio not present in Windows after libgfxinit
449ThinkPad T440p fail to start, continuous beeping & LED blinking
448Thinkpad T440P ACPI Battery Value Issues
446Optiplex 9010 No Post
439Lenovo X201 Turbo Boost not working (stuck on 2,4GHz)
427x200: Two battery charging issues
412x230 reboots on suspend
393T500 restarts rather than waking up from suspend
350I225 PCIe device not detected on Harcuvar

Plans for the next release

  • Finish adding chipset device trees for all SOCs
  • Improve code for options/setup
  • Start reformatting C files with clang-format
  • Add warning/error step for Makefiles at the end

coreboot Links and Contact Information

  • Main Website: https://www.coreboot.org
  • Downloads: https://coreboot.org/downloads.html
  • Source control: https://review.coreboot.org
  • Documentation: https://doc.coreboot.org
  • Issue tracker: https://ticket.coreboot.org/projects/coreboot
  • Donations: https://coreboot.org/donate.html