coreboot changelog Feb 17 – March 1

This changelog covers 105 commits in the two week period between February 17, 2016 and March 1, 2016. (6a622311 – 163506a8)

We’ve entered a lower volume period for patches being submitted, so for a while, blog posts will be every two weeks instead of every week. Once we get above 100 patches a week, blog posts will be weekly again.

Payloads got some attention during this period, adding a way to include additional modules into the GRUB2 build. An option was added to build and include coreinfo as a ‘secondary’ payload, allowing it to be run from another payload. We also added U-Boot as a coreboot payload. This is currently still just in development, and needs additional work before it will act as a generic payload for all platforms.

We added LZ4 compression to the build with runtime decompression for cbfs. LZ4’s speed should be roughly the same as LZMA, trading a smaller compressed size for slightly slower decompressoin. LZ4’s main advantage is that it requires much less memory to do the decompression, allowing for compression of stages that couldn’t previously be compressed.

The suite of board-status scripts got several updates, fixing timestamp handling for the sanitized path names, handling when the script is run as super-user in a better way, and adding a script that will set up a Ubuntu Live-image to allow users to more easily run the board-status script.

In the build tools and utilities, we had some fixes for the toolchain builder, updating the GDB builds for x86_64 and MIPS. A couple of scripts were also added. One utility downloads and extracts binary blobs from Chrome OS recovery images, and the other new script allow easier testing of POST cards.

Intel based boards and chipsets received a large percentage of the patches for the past two weeks:

The Galileo board and Quark chip had several pieces new added, along with additional documentation for those changes. Major pieces done were to set up the basic registers, in the ACPI FADT, setting up the memory map, and enabling the UART.

We received the final set of patches to finish out the changes combining many of the the Intel GPIO initialization routines into a single common set of functions. The autoport script was updated to use the common GPIO functions.

Sandy Bridge / Ivy Bridge memory initialization also continued to receive updates, adding support for XMP profiles in the SPD, updating logging, and fixing some bugs.

Intel’s Skylake chipset and boards were updated to enable Hardware P-state control (HWP) based on Intel’s Speed Shift Technology (SST). Another change to Skylake platforms increased stolen memory for graphics to 64MB.

Intel Bay Trail got a couple of updates, adding a fix for issues with displayport on the FSP version, and adding IOSF access support to the reg_script module.

Intel Apollo Lake had several more foundational pieces added to the codebase. Many more patches for Apollo Lake are expected in the next couple of weeks.

On the non-X86 side, the instructions for running the Arm7 Qemu board were updated, and the memory map was corrected.

RISC-V got a couple of patches, adding additional debugging, and fixing some inline asm code.
The coreboot project would like to recognize another pair of developers who have hit major milestones in the past two weeks:

Lee Leahy just reached his 100th commit merged into Lee is a developer with Intel who has been working on coreboot for about a year and a half. He has worked on many of the recent intel chipsets, and is currently adding support and documentation for the Intel Galileo board and Quark chips in a way that each step of the process can be tested and verified. While this takes significantly more effort than the typical method of porting, it should result in a better platform.

Tobias Diedrich has just had his 50th patch merged.  Tobias has been contributing patches to coreboot for over five years, and his patches have spanned a number of boards and chipsets.

Finally, please welcome our newest authors:
Andrew Waterman contributed the pair of RISC-V patches.
Joe Pillow added the Chrome OS recovery image script.

coreboot statistics

- Total commits: 105
- Total authors: 25
- Total lines added: 13396
- Total lines removed: -3127
- Total difference: 10269

Added 1 mainboard: emulation/qemu-power8
Added 1 processor: qemu-power8

Submodule updates:
- 3rdparty/arm-trusted-firmware (329 commits)
- 3rdparty/vboot (2 commits)

=== Top Authors - Number of commits ===
Leroy P Leahy                20 (19.048%)
Aaron Durbin                 11 (10.476%)
Patrick Rudolph               8 (7.619%)
Patrick Georgi                8 (7.619%)
Martin Roth                   8 (7.619%)
Stefan Reinauer               5 (4.762%)
Vladimir Serbinenko           5 (4.762%)
Denis 'GNUtoo' Carikli        4 (3.810%)
Julius Werner                 4 (3.810%)
Werner Zeh                    4 (3.810%)
Duncan Laurie                 4 (3.810%)
Ronald G. Minnich             4 (3.810%)
Total Authors: 25

=== Top Authors - Lines added ===
Julius Werner              7602 (56.748%)
Leroy P Leahy              1255 (9.368%)
Ronald G. Minnich          1097 (8.189%)
Stefan Reinauer             990 (7.390%)
Werner Zeh                  479 (3.576%)
Patrick Rudolph             406 (3.031%)
Damien Zammit               336 (2.508%)
Martin Roth                 293 (2.187%)
Aaron Durbin                232 (1.732%)
Joseph Pillow               218 (1.627%)

=== Top Authors - Lines removed ===
Stefan Reinauer            1662 (53.150%)
Patrick Rudolph             936 (29.933%)
Julius Werner               154 (4.925%)
Aaron Durbin                128 (4.093%)
Leroy P Leahy                93 (2.974%)
Damien Zammit                21 (0.672%)
Patrick Georgi               20 (0.640%)
Vladimir Serbinenko          17 (0.544%)
Tobias Diedrich              15 (0.480%)
David Hendricks              13 (0.416%)

=== Top Reviewers - Number of patches reviewed ===
Martin Roth                  43 (40.952%)
Stefan Reinauer              33 (31.429%)
Paul Menzel                  30 (28.571%)
Aaron Durbin                 13 (12.381%)
Andrey Petrov                 8 (7.619%)
Furquan Shaikh                8 (7.619%)
Patrick Georgi                6 (5.714%)
Ronald G. Minnich             5 (4.762%)
Timothy Pearson               4 (3.810%)
Patrick Rudolph               3 (2.857%)
Total Reviewers: 18

=== Top Submitters - Number of patches submitted ===
Martin Roth                  40 (38.095%)
Leroy P Leahy                18 (17.143%)
Stefan Reinauer              13 (12.381%)
Patrick Georgi                8 (7.619%)
Aaron Durbin                  8 (7.619%)
Vladimir Serbinenko           5 (4.762%)
Ronald G. Minnich             4 (3.810%)
Julius Werner                 4 (3.810%)
Werner Zeh                    3 (2.857%)
Total Submitters: 11

coreboot changelog Feb 10 – Feb 16

This changelog covers 77 commits in the week between February 10, 2016 and February 16, 2016. (318ef96a – 0188b139)

Many of the big changes this week surrounded native initialization of the Sandy Bridge/Ivy Bridge platforms. We got patches to change platforms which had been previously based on Intel’s MRC blob to build with either the MRC or coreboot’s native memory initialization. We also got patches combining the Intel GPIO initialization for various chipsets into a single common set of functions.

Continuing the series from the past several weeks, we merged patches for the Intel Apollo Lake, Skylake, and Quark platforms. Apollo Lake got a skeleton for its initial mainboard, and added code to support GPIO init. Quark added FSP initialization and MTRR support. The more mature Skylake SoC received some minor fixes for graphics and to finalize SMM inside coreboot.

Another of the Intel FSP platforms, the FSP version of the Intel Bay Trail codebase was updated to support version 5 of the Bay Trail FSP, which should be released to the Intel website shortly.

On the ARM side, we got several small fixes, and a patch to verify consistency of the page table descriptors. This sounds like it will help prevent ‘interesting’ debug sessions due to conflicting memory types for the same memory area.

The build system and toolchain received fixes for issues downloading git submodules, for the gitconfig make target, and for building under paths that have an ‘@’ character in their name. A couple of changes were added to make Kconfig’s strict mode slightly less strict and more user friendly.

Two new lint tools were added this week, one to make sure that the site-local directory doesn’t get pushed and committed, and another that checks over the Kconfig files for various issues.

Other changes this week included a change to allow bootblock code to use CAR_GLOBAL variables, and continued work updating and adding license headers throughout the coreboot codebase.

Finally, I’d like to recognize two contributors this week:

Damien Zammit (damo22) reached his 50th commit merged into coreboot last week. His contributions have included the addition of two complete platforms, the Intel D510MO board with the Intel Pineview Atom processor, and the Gigabyte GA-G41M-ES2L board with the Intel x4x northbridge and Intel i82801gx southbridge. Damien joined coreboot in July of 2013, but has recently become very active.

Vladimir Serbinenko (phcoder) just broke 550 patches merged with his work moving Sandy Bridge/Ivy Bridge MRC platforms to native init mentioned earlier. Vladimir joined coreboot just under 3 years ago, and has been a fantastic contributor to the community.

Thanks to both of you, and to all the rest of the coreboot contributors.

coreboot statistics

- Total commits: 77
- Total authors: 16
- Total lines added: 6494
- Total lines removed: -1569
- Total difference: 4925

Added 1 mainboard: intel/apollolake_rvp

=== Top Authors - Number of commits ===
Patrick Georgi               12 (15.584%)
Vladimir Serbinenko          12 (15.584%)
Aaron Durbin                  9 (11.688%)
Julius Werner                 7 (9.091%)
Andrey Petrov                 6 (7.792%)
Duncan Laurie                 5 (6.494%)
Martin Roth                   5 (6.494%)
Leroy P Leahy                 4 (5.195%)
Alexandru Gagniuc             3 (3.896%)
Patrick Rudolph               3 (3.896%)
Yves Roth                     3 (3.896%)
Stefan Reinauer               3 (3.896%)

=== Top Authors - Lines added ===
Ruilin Hao                 2528 (38.928%)
Andrey Petrov               817 (12.581%)
Vladimir Serbinenko         681 (10.487%)
Yves Roth                   678 (10.440%)
Leroy P Leahy               451 (6.945%)
Patrick Rudolph             355 (5.467%)
Alexandru Gagniuc           242 (3.727%)
Aaron Durbin                213 (3.280%)
Patrick Georgi              194 (2.987%)
Julius Werner               131 (2.017%)

=== Top Authors - Lines removed ===
Vladimir Serbinenko         892 (56.851%)
Aaron Durbin                247 (15.743%)
Julius Werner               244 (15.551%)
Patrick Georgi               68 (4.334%)
Yves Roth                    64 (4.079%)
Martin Roth                  13 (0.829%)
Duncan Laurie                12 (0.765%)
Patrick Rudolph              11 (0.701%)
Andrey Petrov                 7 (0.446%)
Ruilin Hao                    4 (0.255%)

=== Top Reviewers - Number of patches reviewed ===
Martin Roth                  31 (40.260%)
Aaron Durbin                 16 (20.779%)
Patrick Georgi               13 (16.883%)
Paul Menzel                  13 (16.883%)
Alexandru Gagniuc            12 (15.584%)
Stefan Reinauer              11 (14.286%)
FEI WANG                      3 (3.896%)
York Yang                     2 (2.597%)
Andrey Petrov                 2 (2.597%)
Total Reviewers: 15

=== Submitters - Number of patches submitted ===
Martin Roth                  25 (32.468%)
Aaron Durbin                 19 (24.675%)
Patrick Georgi               15 (19.481%)
Vladimir Serbinenko           6 (7.792%)
Stefan Reinauer               6 (7.792%)
Julius Werner                 5 (6.494%)
Ronald G. Minnich             1 (1.299%)
Total Submitters: 7

coreboot changelog Feb 3 – Feb 9

This changelog covers 107 commits in the week between February 3, 2016 and February 9, 2016. (2cc2ff6f – c285b30b)

This week, it looks like the biggest set of changes were the changes directly supporting chrome verified boot, adding options for the GBB flags and supporting VBNV (vboot non-volatile storage) in cmos, flash, and the EC. The verified boot (vboot) submodule included by coreboot was also updated, bringing in another 26 patches. These changes included a variety of work committed to the chromium vboot repo over the past several months. Another submodule was added this week to bring the Chrome EC codebase into the coreboot tree. There were several additional commits to update the build to use the new submodule.

The Intel Skylake and associated boards continued to get updates including more GPIO fixes, disabling the PM timer in ACPI, and unconditionally setting up the BAR for the SPI controller.

Intel continued adding documentation in the Documentation/Intel directory. This is mostly targeting the newly added Galileo mainboard, the newly added Quark X1000 Soc, and version 1.1 of the Intel FSP.

The AMD Family 10h / Family 15h directory and mainboard got some more patches, updating the RDIMM memory training code to work around some failures. The other main feature added was a CMOS option to enable/disable core boost.

There were a number of ACPI ASL changes this week. Several were bugfixes, some were to get rid of unused variables causing warning, and others worked around different warnings generated by new versions of the IASL ACPI compiler. These will help the effort to upgrade the IASL ACPI compiler to the latest version.

The native memory initialization code for the Intel Sandybridge/Ivybridge platforms had a fix for using two DIMMs per channel, and there were a few changes working towards switching the MRC based Sandybridge/Ivybridge implementations over to using native graphics and memory initialization. The goal is that the boards that currently use the Intel MRC should be able to build with either path. More of these changes will be merged in the coming weeks.

The toolchain builder, buildgcc, had several changes to clean up and reorganize the makefiles, and to add a toolchain build for the nds32le architecture in support of the chrome EC builds.

coreboot’s site-local directory was extended to use a Kconfig file and adds a make target which gets run at the end of the rest of the build. Documentation on how to use this should be completed and released next week.

Miscellaneous other fixes include a new lint test ensuring assembly is in AT&T syntax, an update to the QT version for the ‘xconfig’ Kconfig front end, adding PS/2 Aux presence detect to the nuvoton nct5572d SuperIO, and adding a new ARM SoC, Marvell’s Armada 38x.

Thank you to everyone who contributes to the coreboot community.

New issues that we saw this week

– The toolchain build seems to be broken for some people as of commit 8e68aff51 – “buildgcc: enable multilib for gcc”
– There were issues with make gitconfig on a newly cloned repo caused by commit ec0b586 – “3rdparty/chromeec: Add Chrome EC firmware sources”.
– Commit ec0b586 – “3rdparty/chromeec: Add Chrome EC firmware sources” also causes issues pulling down the blobs submodule.

New bugs filed this week

– board-status allows invalid uploads
– Windows doesn’t like ToString() calls in ACPI
– [Haswell/Broadwell] LPC power optimizer RCBA instructions break eDP display with Intel VBIOS
– cbmem utility fails on newer linux kernels “Failed to mmap /dev/mem: Resource temporarily unavailable”
– Provide and use enums for SerialIoI2cVoltage

coreboot statistics for the past week

- Total commits: 107
- New authors: 3
- Total authors: 24
- Total reviewers: 14
- Total lines added: 13759
- Total lines removed: -1974
- Total difference: 11785

Added 2 mainboards: asus/kcma-d8 & intel/galileo
Added 1 mainboard variant: lenovo/X220i
Added 2 SoCs: intel/quark & marvell/armada38x

=== Top Authors - Number of commits ===
Leroy P Leahy                15 (14.019%)
Patrick Georgi               15 (14.019%)
Aaron Durbin                 14 (13.084%)
Vladimir Serbinenko          10 (9.346%)
Timothy Pearson               8 (7.477%)
Duncan Laurie                 7 (6.542%)
Martin Roth                   6 (5.607%)
Stefan Reinauer               6 (5.607%)
Ruilin Hao                    5 (4.673%)
Total Authors: 25

=== Top Authors - Lines added ===
Timothy Pearson            3956 (28.752%)
Ruilin Hao                 2964 (21.542%)
Leroy P Leahy              2780 (20.205%)
Duncan Laurie              1091 (7.929%)
Zheng Bao                   463 (3.365%)
Dhaval Sharma               450 (3.271%)
Patrick Georgi              397 (2.885%)
Aaron Durbin                397 (2.885%)
Lee Leahy                   346 (2.515%)
Edward O'Callaghan          236 (1.715%)

=== Top Authors - Lines removed ===
Zheng Bao                   426 (21.581%)
Edward O'Callaghan          393 (19.909%)
Duncan Laurie               323 (16.363%)
Timothy Pearson             223 (11.297%)
Vladimir Serbinenko         108 (5.471%)
Stefan Reinauer             106 (5.370%)
Aaron Durbin                 84 (4.255%)
Pratik Prajapati             79 (4.002%)
Martin Roth                  62 (3.141%)
Patrick Georgi               49 (2.482%)

=== Top Reviewers - Number of patches reviewed ===
Martin Roth                  55 (51.402%)
Stefan Reinauer              44 (41.121%)
Aaron Durbin                  8 (7.477%)
FEI WANG                      6 (5.607%)
Patrick Georgi                6 (5.607%)
Paul Menzel                   5 (4.673%)
Timothy Pearson               2 (1.869%)
Leroy P Leahy                 2 (1.869%)
Alexander Couzens             2 (1.869%)
Felix Held                    2 (1.869%)
Total Reviewers: 14

=== Submitters - Number of patches submitted ===
Patrick Georgi               44 (41.121%)
Martin Roth                  37 (34.579%)
Stefan Reinauer              13 (12.150%)
Leroy P Leahy                11 (10.280%)
Vladimir Serbinenko           2 (1.869%)
Total Submitters: 5

coreboot changelog Jan 27 – Feb 2

This changelog covers 131 commits in the week between January 27, 2016 and February 2, 2016. (dd4b66e2 – 95909924)

The biggest news of the past week was getting the 4.3 release done. The 4.4 release should come towards the end of April.

Of particular note to anyone submitting patches, we added 2 new code checkers this week, one to verify that the executable bit isn’t set on source files, and one to verify that the standard coreboot license header is used on files using the GPL 2 or 2+ licenses. These checks will be run automatically when you commit code if you have the git commit hook in place, and will also be run on the build server.

coreboot again had numerous patches surrounding the build system, tools, and utilities. The flood of cbfstool related patches finally slowed a bit, but we still had some cleanup, both in the tool and in the cbfs sections of the Makefiles. In the toolchain area, we updated LLVM to version 3.7.1, and added GNU Make to the toolchain. The addition of make was to address some upcoming patches that needed the newer version, as well as to support platforms that don’t install GNU make by default. The kconfig_lint tool had various updates to get rid of warnings that we don’t care about, to add documentation, and to add a couple of additional checks. Next week will see a few more fixes, and it will be put in place as a stable lint tool.

We had significant updates to a number of mainboards and the related chipsets in the past week as well. Intel had a large number of changes for their Braswell SoC and its reference board, Strago, merged this week. These included fixes for GPIOs, clocks, SD cards, and thermal support, as well as FSP integration updates. The Asus kgpe-d16 mainboard, along with the AMD Fam10h-Fam15h processor directory and the SB700 soutbridge had numerous patches to improve stability, fix IRQ routing and APIC identification, and improve ACPI. The winbond w83667hg-a was added to the coreboot codebase for the board as well. The Intel d510mo board had some improvements related to native graphics initialization, GPIOs and ACPI. The gigabyte ga-g41m-es2l and the Intel x4x northbridge code had some general cleanup and improvements to cbmem and memory initialization. We also saw the introduction of the initial framework for the new Intel Apollo Lake SoC. We’ll be seeing many more patches related to Apollo Lake in the coming weeks.

Other changes of note included code to initialize the PS/2 aux port, a way to access memory address 0 without GCC “optimizing” it into a crash, and the addition of some documentation from Intel about developing new FSP based boards and chipsets. Finally, the Intel sklrvp Skylake reference board was dropped in favor of using the kunimitsu board.

coreboot statistics for the past week

- Total commits: 131
- New authors: 8
- Total authors: 30
- Total lines added: 3833
- Total lines removed: -3652
- Delta: 181

=== Top Authors - Number of commits ===
Timothy Pearson              22 (16.794%)
Martin Roth                  21 (16.031%)
Patrick Georgi               15 (11.450%)
Damien Zammit                13 (9.924%)
Hannah Williams              12 (9.160%)
Leroy P Leahy                 5 (3.817%)
Stefan Reinauer               5 (3.817%)
Divagar Mohandass             4 (3.053%)
Vladimir Serbinenko           3 (2.290%)
Alexandru Gagniuc             3 (2.290%)
Total Authors: 31

=== Top Authors - Lines added ===
Damien Zammit               725 (18.915%)
Timothy Pearson             701 (18.289%)
Leroy P Leahy               646 (16.854%)
Subrata Banik               427 (11.140%)
Martin Roth                 262 (6.835%)
Aaron Durbin                204 (5.322%)
Patrick Georgi              179 (4.670%)
Alexandru Gagniuc           140 (3.652%)
shkim                       107 (2.792%)
Nico Huber                   91 (2.374%)

=== Top Authors - Lines removed ===
Martin Roth                1688 (46.221%)
Hannah Williams             661 (18.100%)
Divagar Mohandass           315 (8.625%)
Damien Zammit               307 (8.406%)
Timothy Pearson             212 (5.805%)
Patrick Georgi              104 (2.848%)
Nico Huber                  102 (2.793%)
Leroy P Leahy                95 (2.601%)
Stefan Reinauer              43 (1.177%)
Lee Leahy                    23 (0.630%)

=== Top Reviewers - Number of patches reviewed ===
Martin Roth                  71 (54.198%)
Stefan Reinauer              20 (15.267%)
Patrick Georgi               18 (13.740%)
Paul Menzel                  16 (12.214%)
Alexandru Gagniuc            14 (10.687%)
Aaron Durbin                 10 (7.634%)
Felix Held                    8 (6.107%)
Timothy Pearson               7 (5.344%)
Nico Huber                    4 (3.053%)
Alexander Couzens             3 (2.290%)
Total Reviewers: 15

=== Top Submitters - Number of patches merged ===
Martin Roth                  94 (71.756%)
Patrick Georgi               15 (11.450%)
Stefan Reinauer               8 (6.107%)
Leroy P Leahy                 6 (4.580%)
Vladimir Serbinenko           3 (2.290%)
Nico Huber                    2 (1.527%)
Aaron Durbin                  2 (1.527%)
Werner Zeh                    1 (0.763%)
Total Submitters: 8

Announcing coreboot 4.3

The “Oh, has FOSDEM started?” release
Dear coreboot community,

today marks the release of coreboot 4.3, the third release on our time based release schedule.
Since the last release, 1030 commits by 114 authors added a net total of 17500 lines to the source code. Thank you to all who contributed!

The release tarballs are available at There’s also a 4.3 tag and branch in the git repository.

Besides the usual addition of new mainboards (14) and chipsets (various), a big theme of the development since 4.2 was cleaning up the code: 20 mainboards were removed that aren’t on the market for years (and even hard to get on Ebay). For several parts of the tree, we established tighter controls, making errors out of what were warnings (and cleaning up the code to match) and provided better tests for various aspects of the tree, and in general tried to establish a more consistent structure across the code base.

Besides that, we had various improvements across the tree, each important when using the hardware, but to numerous for individual shout outs. Martin compiled a list that’s best posted verbatim. Thanks Martin!

Log of commit 529fd81f640fa514ea4c443dd561086e7c582a64 to commit 1bf5e6409678d04fd15f9625460078853118521c for a total of 1030 commits:


Added 14 mainboards

– asus/kfsn4-dre_k8: Native init Dual AMD K8 CPUs & Nvidia CK804 southbridge
– esd/atom15: Bay Trail SOC mainboard using Intel’s FSP
– gigabyte/ga-g41m-es2l: Intel Core 2 / Native init x4x NB / I82801GX SB
– google/guado: Intel Broadwell chromebox (Asus Chromebox CN62)
– google/oak: Mediatek MT8173 SoC chromebook
– google/tidus: Intel Broadwell chromebox (Lenovo ThinkCentre Chromebox)
– google/veyron_emile: Rockchip RK3288 SoC board
– intel/d510mo: Native init Intel Pineview with Intel I82801GX southbridge
– intel/littleplains: Intel Atom c2000 (Rangeley) SoC board
– intel/stargo2: Intel Ivy Bridge / Cave Creek usint Intel’s FSP
– lenovo/r400: Intel Core 2 / Native init GM45 NB / Intel I82801IX SB
– lenovo/t500: Intel Core 2 / Native init GM45 NB / Intel I82801IX SB
– purism/librem13: Intel Broadwell Laptop using Intel MRC
– sunw/ultra40m2: Native init Dual AMD K8 Processors & Nvidia MCP55 SB

Removed 20 mainboards

– arima/hdama
– digitallogic/adl855pc
– ibm/e325, e326
– intel/sklrvp
– iwill/dk8s2, dk8x
– newisys/khepri
– tyan/s2735, s2850, s2875, s2880, s2881 & s2882
– tyan/s2885, s2891, s2892, s2895, s4880 & s4882

Improvements to mainboards

– amd/bettong: fixes to Interrupts, Memory config, S4, EMMC, UARTS
– asus/kgpe-d16: IOMMU and memory fixes, Add CMOS options, Enable GART
– intel/strago: GPIO, DDR, & SD config, FSP updates, Clock fixes
– ACPI fixes across various platforms
– Many individual fixes to other mainboards

Continued updates for the Intel Skylake platform

– google/chell, glados, & lars: FSP & Memory updates, Add Fan & NHLT support
– intel/kunimitsu: FSP & GPIO updates, Add Fan & NHLT (audio) support

Build system

– Update build to use FMAP based firmware layout with multiple cbfs sections
– Enable Kconfig strict mode – Kconfig warnings are no longer allowed.
– Enable ACPI warnings are errors in IASL – warnings are no longer allowed.
– Tighten checking on toolchains and give feedback to users if there are issues
– Updates to get the ADA compiler to work correctly for coreboot
– Various improvements to Makefiles and build scripts
– Cleanup of CBFS file handling


– cleanups and improvements to many of the utilities
– cbfstool: Many fixes and extensions to integrate with FMAP
– Add amdfwtool to combine AMD firmware blobs instead of using shell scripts.
– Toolchain updates: new versions of GMP & MPFR. Add ADA.
– Updates for building on NetBSD & OS X


– SeaBIOS: Update stable release to 1.9.0
– coreinfo: fix date, hide cursor, use crosscompiler to build
– libpayload: updates for cbfs, XHCI and DesignWare HCD controllers


– Added 1 soc: mediatek/mt8173
– Various fixes for ARM64 platforms


– Added 2 northbridges: intel/pineview & x4x
– Removed 1 northbridge: intel/i440lx
– Added 1 southbridge: intel/fsp_i89xx
– Removed 2 southbridge(s): intel/esb6300 & i82801cx
– Rename amd/model_10xxx to family_10h-family_15h.
– ACPI: fix warnings, Add functions for IVRS, DMAR I/O-APIC and HPET entries
– Work in many areas fixing issues compiling in 64-bit
– Numerous other fixes across the tree

Areas with significant work on updates and fixes

– cpu/amd/model_fxx
– intel/fsp1_x: Fix timestanps & postcodes, add native CAR & microcode
– nb/amd/amdfam10: Add S3, voltage & ACPI, speed fixes & MANY other changes
– nb/amd/amdmct: Add S3, mem voltage, Fix performance & MANY other changes
– nb/intel/sandybridge: Add IOMMU & ACPI DMAR support, Memory cleanup
– soc/intel/braswell: FSP & ACPI updates, GPIO & clock Fixes
– soc/intel/fsp_baytrail: GPIO, microcode and Interrupt updates.
– soc/intel/skylake: FSP, Power/Thermal & GPIO Updates, Add NHLT support
– sb/amd/sb700: Add ACPI & CMOS Setting support, SATA & clock Fixes


– Imgtec Pistachio: Memory, PLL & I2C fixes, add reset


– Expand functionality for ite/it8718f & nuvoton/nct5572d superio devices

Added 3 SIOs

– intel/i8900
– winbond/w83667hg-a & wpcd376i

Removed 6 SIOs

– fintek/f71889
– ite/it8661f
– nsc/pc8374 & pc97307
– nuvoton/nct6776
– smsc/fdc37m60x


– Several updates for reading EDID tables


– Commonlib: continued updates for cbfs changes
– Work on getting license headers on all coreboot files
– Drop the third paragraph of GPL copyright header across all of coreboot


3rdparty/blobs: Update to CarrizoPI (Binary PI 1.5)

coreboot statistics

Total commits: 1030
Total authors: 114
New authors: 46
Total Reviewers: 41
Total lines added: 88255
Total lines removed: -70735
Total delta: 17520

coreboot changelog Jan 20 – Jan 26

This changelog covers 111 commits in the week between January 20, 2016 and January 26, 2016. (aad9b6a – 7ee6cd5)

There was another large set of patches continuing the work that has been done extending cbfs and integrating FMAP.  This series is expected to be finished in just a few more patches.

This past week saw the addition of two new mainboards – the Google Tidus board (Lenovo ThinkCentre Chromebox), and the Purism Librem 13 laptop.  Updates to the Google Oak board and its associated SoC, the Mediatek MT8173 Cortex A72, accounted for roughly 20% of this week’s changes.

The AMD native memory initialization for the family10h/family15h chips had more changes, with still more coming next week.  On the Intel side, the Pineview northbridge saw a couple of updates, and there were several fixes for for Intel’s Braswell and Skylake chips.

coreboot also had some more toolchain updates this week, adding an ada compiler for some upcoming work, and getting the gcc build set up for the Power8 work.  There were also a couple of fixes for building tools under NetBSD

In the coming week, we should get the 4.3 release finished, and see a slew of changes as the patches that are currently in review get merged.

coreboot statistics for the past week

- Total commits: 111
- New authors: 11
- Total authors: 36
- Total lines added: 10885
- Total lines removed: -604
- Delta: 10281

=== Authors - Number of commits ===
Patrick Georgi       15 (13.514%)
Martin Roth          11 (9.910%)
Nico Huber            8 (7.207%)
Timothy Pearson       8 (7.207%)
Duncan Laurie         7 (6.306%)
Alexandru Gagniuc     6 (5.405%)
Werner Zeh            5 (4.505%)
Damien Zammit         4 (3.604%)
Itamar                4 (3.604%)
Yidi Lin              3 (2.703%)
Felix Durairaj        3 (2.703%)
Koro Chen             3 (2.703%)
Aaron Durbin          3 (2.703%)
Total Authors: 36

=== Authors - Lines added ===
Matt DeVillier     2456 (22.563%)
Patrick Georgi     1968 (18.080%)
Duncan Laurie      1264 (11.612%)
Timothy Pearson    1260 (11.576%)
Tianping Fang       505 (4.639%)
Liguo Zhang         460 (4.226%)
Leilk Liu           418 (3.840%)
David Hendricks     395 (3.629%)
Chunfeng Yun        368 (3.381%)
Subrata Banik       321 (2.949%)

=== Authors - Lines removed ===
Patrick Georgi      158 (26.159%)
Timothy Pearson     137 (22.682%)
Aaron Durbin         75 (12.417%)
Stefan Reinauer      30 (4.967%)
Martin Roth          25 (4.139%)
Nico Huber           24 (3.974%)
Alexandru Gagniuc    23 (3.808%)
T.H.Lin              21 (3.477%)
Damien Zammit        20 (3.311%)
Duncan Laurie        20 (3.311%)

=== Reviewers - Number of patches reviewed ===
Martin Roth          48 (43.243%)
Stefan Reinauer      28 (25.225%)
Patrick Georgi       26 (23.423%)
Paul Menzel          17 (15.315%)
Alexandru Gagniuc    12 (10.811%)
Aaron Durbin         12 (10.811%)
Ronald G. Minnich     5 (4.505%)
Nico Huber            2 (1.802%)
Timothy Pearson       2 (1.802%)
Felix Held            2 (1.802%)
Total Reviewers: 17

=== Submitters - Number of patches merged ===
Patrick Georgi       58 (52.252%)
Martin Roth          30 (27.027%)
Aaron Durbin          7 (6.306%)
Nico Huber            6 (5.405%)
Werner Zeh            5 (4.505%)
Stefan Reinauer       3 (2.703%)
Duncan Laurie         2 (1.802%)
Total Submitters: 7

coreboot changelog Jan 5 – Jan 19

This changelog covers the 180 commits between January 5, 2016 and
January 19, 2016.  (af91b8b0 – 967881d0)

We’re preparing for the coreboot 4.3 release, expected to happen sometime in the next week, so there has been a lot of activity surrounding Intel’s Skylake chips, both in the mainboards and SOC directories. The Skylake and braswell platforms are finally being build-tested by jenkins, which will help keep the platforms working.

The changes in cbfstool are continuing to roll in, although this should be wrapping up before long as the merger of cbfs with FMAP is completed.

The effort to standardize coreboot’s license headers across all files is just starting, and will be going on for a few weeks as we verify that all source files have the correct headers.  We’ve added and improved the lint checkers for these so expect failures from jenkins if files with non-compliant headers are pushed.

A fair amount of work was done in the build system in the past couple of weeks.  This removed the warnings about cross compilers not existing unless that architecture is currently being built, fixed some dependency issues, and fixed several other minor issues. A make target to check the versions of the coreboot toolchain was also added.

We had a slight toolchain change, going to MPFR version 3.1.3 to fix some issues seen on the upcoming Power8 processor.

Additional changes added NetBSD support for various utilities, and update the intel/gm45 and intel/pineview northbridges.

Added 1 mainboard:
– google/guado

coreboot statistics
– Total commits: 180
– New authors: 13
– Total authors: 45
– Total reviewers: 19
– Total lines added: 9168
– Total lines removed: -2130
– Total difference: 7038

=== Authors – Number of commits ===
Martin Roth                  56 (31.111%)
David Wu                     15 (8.333%)
Aaron Durbin                 12 (6.667%)
Duncan Laurie                 9 (5.000%)
Subrata Banik                 8 (4.444%)
Rizwan Qureshi                7 (3.889%)
Nico Huber                    6 (3.333%)
Patrick Georgi                6 (3.333%)
Timothy Pearson               5 (2.778%)
Barnali Sarkar                5 (2.778%)
Total Authors: 45

=== Authors – Lines added ===
Martin Roth                2359 (25.731%)
Matt DeVillier             2243 (24.466%)
Aaron Durbin               1988 (21.684%)
Rizwan Qureshi              606 (6.610%)
Subrata Banik               292 (3.185%)
Barnali Sarkar              178 (1.942%)
robbie zhang                158 (1.723%)
Nico Huber                  144 (1.571%)
Andrey Korolyov             133 (1.451%)
David Wu                    128 (1.396%)

=== Authors – Lines removed ===
Martin Roth                1038 (48.732%)
Barnali Sarkar              173 (8.122%)
Aaron Durbin                144 (6.761%)
Nico Huber                  108 (5.070%)
Patrick Georgi               98 (4.601%)
Shaunak Saha                 81 (3.803%)
Paul Menzel                  69 (3.239%)
Patrick Rudolph              68 (3.192%)
Subrata Banik                64 (3.005%)
Duncan Laurie                61 (2.864%)

=== Reviewers – Number of patches reviewed ===
Martin Roth                  91 (50.556%)
Stefan Reinauer              43 (23.889%)
Patrick Georgi               43 (23.889%)
Paul Menzel                  23 (12.778%)
Alexandru Gagniuc            13 (7.222%)
Nico Huber                    7 (3.889%)
York Yang                     3 (1.667%)
Werner Zeh                    3 (1.667%)
Aaron Durbin                  3 (1.667%)
Total Reviewers: 19

=== Submitters – Number of patches submitted ===
Martin Roth                  89 (49.444%)
Patrick Georgi               73 (40.556%)
Aaron Durbin                  9 (5.000%)
Stefan Reinauer               4 (2.222%)
Vladimir Serbinenko           3 (1.667%)
Werner Zeh                    1 (0.556%)
Nico Huber                    1 (0.556%)
Total Submitters: 7

coreboot changelog

The week leading up to November 15th has seen 132 commits (8bd1c36..3ca4116).
The leading themes were the removal of support for old mainboards, and the integration of more non-AGESA AMD support code for Family 10h to 15h that spans everything from fixes to memory configuration to workarounds to problems in the SATA controller, to new feature development, enabling CC6 power-state support and everything in-between.

Other chipset level contributions provided bug fixes to the drivers supporting Intel’s Skylake and AMD’s newer chipsets and mainboards (Kabini, Merlin Falcon, Mullins). Rockchip RK3288 now properly configures displays whether they’re connected through HDMI or DVI.

ARM/ARM64 saw some cleanup in its transition between stages to accommodate more processor configurations on ARM64 SoCs (that sometimes come with smaller 32bit cores for supporting purposes).

Also new is the Intel i8900 southbridge support that can be used with Sandy Bridge and Ivy Bridge, with an Intel reference board, the stargo2, and the SUNW Ultra40m2 board support.

The USB device mode driver for DesignWare’s USB2 controller (DWC2) in libpayload became more robust. The other notable field of work in libpayload is work with PDcurses’ upstream to synchronize their development and our copy.

In terms of the ongoing efforts to clean up old cruft across the entire tree, references to the getpir utility were dropped, after the tool was removed nearly two years ago. We also removed empty mainboard driver files that used to be required by the build system, even if the mainboard needed no special handling in its ramstage.
To help keep the quality bar high, automated testing now also covers intelvbttool. Another forward-looking addition is a clang-format specification of our coding style. It isn’t complete yet, but the hope is that we can eventually use it to simplify adhering to a consistent style and then enforce it.
The script to help organizing the commit log for release notes was pushed into util/release.

coreboot changelog

This changelog covers the week up to November 8th, spanning 63 commits (f6dc544..8bd1c36).

Last week’s code submissions gave us a lot of improvements pretty much everywhere, but the most user-visible change is probably the addition of ACPI S3 support to asrock/e350m1.

Speaking of ACPI, support for the DMAR tables used to report Intel IOMMU (VT-d) information to the operating system was significantly improved and is enabled on Sandy Bridge and Ivy Bridge.

Another user visible change is the rework of the fallback mechanism in our bootblock, making its CMOS-backed state handling more robust.

cbmem also saw some changes in that all its entries are now listed separately in cbtables (and util/cbmem uses that new structure) to cut down on what coreboot exposes as interface.

On the architectures side, ARM64 dropped its sec(urity) mon(itor) code in favor of using ARM Ltd’s Open Source arm-trusted-firmware, which we already import in 3rdparty.

The integration of commits to support AMD Fam15h CPUs with a non-AGESA implementation that integrates better with coreboot saw some progress. The AMD Binary PI side saw a number of bug fixes, too.

Boards based on Intel’s Skylake architecture also saw more development.

In addition to these targetted developments, there was also the usual set of bug fixes across the entire tree, providing some cleanups to the code and configuration system, some portability fixes for Windows and Mac OS X, deduplication of ACPI table generation on i945, and the removal of a Super IO that wasn’t used by any board (and thus isn’t even build tested).

The USB device mode driver in libpayload for the DesignWare USB2 controller works better under debugging, while the XHCI USB3 host controller driver gained a workaround for Intel XHCI controllers.

Finally, the board-status scripts that parse boot success reports into the list of supported motherboards on the wiki were modified to point out more clearly that the list on the wiki describes the current status. This became necessary because some users assumed that it’s outdated.
Since the i440bx mainboards that were at the top of the list may have contributed to that impression, desktop boards were moved down in favor of notebooks and server boards where most of the current development happens.

coreboot changelog

This changelog covers 2 weeks up to November 1st, during which coreboot-4.2 was released.
In that timeframe, the repository saw 214 commits spanning d98471c..f6dc544.

Before we get to the stuff that the tech media gets excited about, the first thing to report about is a bunch of efforts to improve the reliability of our tree and the automated testing we conduct.
abuild, the utility for automatically building the default configuration of every board in the tree, learned to deal with mainboard directories that cover multiple variants of a board. This brings back build test coverage for google/veyron.
Various programs in the util/ hierarchy of the tree are now automatically tested by our build test infrastructure, and the related code saw some refactoring to make testing more tools really simple. During that development, some Makefiles below util/ were also cleaned up.
Another area of clean ups was the conversion of `#ifdef` statements to using the `IS_ENABLED` macro. This ensures that even unused code paths are syntactically validated before the optimizer drops them, leading to the same binary output with better build test coverage.
In preparation of future improvements, we gained a lint tool for Kconfig files. It will be hooked up to the build system once the tree is clean, until then it provides a way to see what’s still missing. Check out `util/lint/kconfig_lint` if you’re curious.
As a proof of concept, util/fuzz-tests now provides an environment to test the jpeg decoder we ship for splash screens using afl-fuzz. The same approach can be applied to other coreboot components to find potential crash bugs (or worse).
Finally, several chip drivers were removed because they had no user in the tree anymore and thus saw no testing at all. Some of them will likely come back together with new mainboards that use them.
In addition to the code development to improve code quality, `util/scripts/maintainers.go` provides a way to query the MAINTAINERS database that we’re building, as one piece of a larger effort to improve code quality through formal submodule maintainership.
Another formal clean-up was the tree-wide removal of the last paragraph of the GPL license header in files, the one denoting where to obtain the license text. First, we ship it in the tree, second, it’s probably easier to get with a quick search engine request than by writing a letter to a US post address that may or may not be current.

Rockchip’s RK3288 gained support for additional power/clock states and a more robust EDID handling.
The ongoing effort to support booting in long mode (64 bit) on AMD64 progressed by the integration of changes to make SMM handling and AMD chipset drivers 64bit clean.
Some ACPI for older Intel chipsets was consolidated and is now used for multiple chipset generations.
The Intel GMA driver has also seen improvements, allowing brightness levels for laptop panels to be configured per board, and to disable the graphics chip entirely.
In terms of drivers, the aspeed driver provides native VGA text, and there were improvements to superio and i2c chip drivers, supporting more of their features.
Sandybridge now initializes CPUs serially for robustness reasons, and Intel FSP supports loading microcode from coreboot.

cbfstool now extracts stages and rmodules as ELF files, including relocation information for the former, so that roundtrips of add-stage/extract/add-stage become possible. It now also compiles more reliably on Cygwin.

libpayload saw the additional of a graphics library to layout images on a framebuffer using framebuffer independent coordinates, and some bug fixes to its USB drivers.

In addition to all those cleanups and little new features, coreboot also provides support for a couple new boards, in particular two Intel Skylake based boards by Google (google/chell and google/lars) as well as Asus KFSN4-DRE with K8 CPUs and Asus KGPE-D16 with more recent AMD CPUs (Fam10h and Fam15h).
All related chipsets also saw significant improvements, of which the still ongoing effort to provide non-AGESA implementations for the Fam15h CPU, as well as a ton (metric, in case you’re curious) of bugfixes and feature developments (for example Suspend to RAM) for all AMD CPUs starting with K8 is particularly notable.

Besides those changes, and minor (but valuable) contributions to improve the code style, there’s a bucket list of improvements across the entire tree: more robust SMM entry on i945, fixes to our SMBIOS table generation, changes to the resource allocator to become more robust and IOMMU friendly and to measure the time it takes, and improvements to the robustness of our build process.