Hi all. Welcome to my midterm report for project “porting coreboot to ARM”.
The goal of this project is porting coreboot to ARM and taking advantage of coreboot’s strength in properly configuring PCI, SAS, SATA and SCSI devices; fast boot times; and payload support.
For ARM SOCs, the device configuring is much easier than that for X86. Most device controllers are connected through the on-chip bus. So the mainly work is focus on porting the basic layout and helping tools to ARM architecture, including CBFS, cbfstool and the codes helping loading next stage and payload into ram.
Changes to this project
At first, I want to work on Marvell ARM SOCs with PCIE support, but after checking into it, I found that mostly all the information and SDK of Marvell SOCs are covered under an NDA license. So I moved to VersatilePB from Armltd.
What works now
- CBFS record the architecture information in the master header
- cbfstool can detect the architecture of a rom file
- cbfstool can create an ARM rom file with bootblock
- bootblock for VersatilePB is ready for use
- romstage code for VersatilePB has been written
What doesn’t work (yet)
- cbfstool can not add-stage to the romfile due to a problem in prase_elf_to_stage
- romstage for VersatilePB has not been tested
- ramstage code for VersatilePB has not been written
What needs work
- design the information struct of hardware for payload on ARM
In this week, I will try to fix the problem of add-stage on ARM and test the romstage code.
Got any feature suggestions/ideas ?