This report covers commits 2f953d3 to b142b84afb, up to early Monday, 2015-10-05
Last week has seen the removal of FSP support for Sandybridge and Ivy Bridge, in favor of the native raminit code and the originally supported MRC binary, with the native code path becoming the default code path on these chipsets.
The microcode handling was reworked further so that Intel microcode is now stored as binary files in 3rdparty/blobs, instead of being kept in the coreboot tree and processed by the compiler.
Development on cbfstool continued, adding the capability to relocate FSP binaries on add, and the capability to store hashes of file data to the file header, which can be a useful primitive for a verified boot process.
For this, the recently introduced commonlib was used to share code between coreboot and cbfstool.
The verstage code for Chrome OS’ vboot was refactored to allow this separate verification stage on x86. verstage was introduced to allow moving the romstage to updateable storage (that can be used only after verification which is what verstage is doing), and the idea is to make this also available on x86.
The change allowed code deduplication for several ARM chipsets, too.
For this, our Cache-as-RAM initialization code also became more independent from romstage code.
Kconfig’s strict mode (akin to gcc’s “warnings-as-errors”) is now available in more of its frontends. This should help fix Kconfig issues.
Several bug fixes also made it in, improving support for older gcc versions, for building on Mac OS X, to get native VGA init to build again for multiple Intel chipsets and more.