Results of the coreboot “Mailing List vs Forum” poll

A little while back, there were a few requests to switch from the mailing list format to a web-based forum for our official communication channel.  The coreboot leadership wanted to see what the actual preferences of the coreboot community was, so I posted a poll.  The poll was publicized in IRC and on the mailing list itself, so should have been communicated to the people who would be most directly affected by any change.

Poll results

Here are the overall results from all responses:

Hate Mailing List:1, Prefer Forum: 6, Don't care: 2, Prefer Mailing list: 21, Hate Forum: 26

We had a total of 60 valid responses, and I think the overall results pretty clearly indicate that the coreboot project should NOT move away from the mailing list.

One suggestion was to split the communication into the mailing list for Developers, and a forum for non-developers. To see what the various groups thought, I made a few more charts:

Developer preferences:

Prefer Forum: 1, Prefer Mailing list: 16, Hate Forum: 15, Other: 3
Developer Responses

So not unexpectedly, the coreboot developers even more overwhelmingly prefer the mailing list to the general results

Non-developer preferences:

Hate Mailing list: 1, Prefer Forum: 5, Don't care: 2, Prefer Mailing list: 5, Hate Forum: 11, Other: 1
Non-developer Responses

So even within the non-developer group, there was a definite preference for the mailing list format.

Finally, I broke the Non-developer group down into the group that said they were coreboot users, as opposed to those that mainly read the mailing list.

coreboot users (non-developers):


Hate Mailing list: 1, Prefer Forum: 4, Prefer Mailing list: 4, Hate Forum: 5
coreboot Users (Non-Developers)

That group had the highest percentage of people who preferred the forum, but it was still well under 40%.


We also asked people what we should do to improve the mailing list.  Here’s a summary of the suggestions:

  • Show people how to set up their (or a different) email client to make reading the mailing list easier.
  • Have people be more polite.
  • Add a FAQ showing previously asked question and answers.
  • A netiquette should be established like on the Linux kernel mailing list.
  • Several suggestions to improve the coreboot mailing list archive at
    • Fix the archive so that long threads aren’t spread into different sections by months.
    • Add a search function to the archive
    • Create monthly archives that can be downloaded (This exists.)
    • Update from Pipermail to a more modern archiver like Hyperkitty –

Since it doesn’t look like we’re going to switch to a forum, I’m not going to list the suggestions that people had for that.


Over the upcoming weeks, we’ll look at our options, and discuss our options and plans in the bi-weekly coreboot community meetings.


My coreboot mug filled with Lefthand Milk stout Nitro.

coreboot is joining the Software Freedom Conservancy

The coreboot project applied to join the Software Freedom Conservancy and has been approved for membership by their board.  There is still some work to be done in hammering out the governance details, but we hope to have everything completed by April.

Joining the SFC as coreboot’s fiscal sponsor will allow us to go forward with fundraising, and that all donations to the coreboot project from the United States will be tax-deductible to the extent permitted by law.  Up to this point, coreboot hasn’t had any official way to accept donations or payments.  This has meant that the project was mainly supported financially by members of the coreboot leadership, which has put some limitations on what we were able to do.

Another of the things that joining the SFC means is that we will be formalizing and fully documenting the coreboot leadership structure.  This is one of the Conservancy’s requirements, and something that they will help the project with.

The Conservancy offers a number of other services to its members. We encourage everyone to take a look at the SFC, and to consider joining as individual supporters.

Announcing coreboot 4.5

We are happy to announce the release of coreboot 4.5

The 4.5 release covers commit 80a3df260767 to commit 0bc12abc2b26.

This release is the first since the project switched from doing quarterly releases to doing biannual releases.  The next release will be in April of 2017.

Since the last release in April, the coreboot project has had 1889 commits by 119 authors.

The release tarballs and gpg signatures are available in the usual place at

There is a 4.5 tag in the git repository, and a branch will be created as needed.

Areas with significant updates:

  • Toolchain (29 commits)
    • Updated mpfr version from 3.1.3 to 3.1.4
    • Updated gcc version from 5.2.0 to 5.3.0
    • Updated binutils version from 2.25 to 2.26.1 & Fix aarch64 build problem
    • Updated gdb version from 7.9.1 to 7.11
    • Updated iasl version from 20160318 to 20160831
    • Updated python version from 3.4.3 to 3.5.1
    • Updated expat version from 2.1.0 to 2.1.1
    • Updated llvm / clang version from 3.7.1 to 3.8.0
    • Updated make version from 4.1 to 4.2.1
  • Build system (32 commits)
    • Updates for cbfstool / fmap changes
    • Order per-region files to optimize placement success
    • Add support for the ADA language and toolchain.
  • Utilities (103 commits)
    • Lint – Update, add tools  to find non-ascii & unprintable chars and to verify a single newline at the end of files
    • cbfstool – Update for Linux payloads, Honor FSP modules addresses, fix elf parsing
    • Sconfig – Add 10 bit addressing mode for i2c devices, add generic device type, support strings, pass in devicetree filename
  • General code cleanup (197 commits)
    • Cleaning up code formatting and whitespace
    • Fix spelling & capitalization
    • Removing commented out code
    • Transition away from device_t
  • TPM (55 commits)
    • Add support for Trusted Platform Module 2.0
    • SPI & refactored I2C TPM driver
  • Drivers (54 commits)
    • Add ACPI support in several drivers
    • coreboot_tables –  Extend serial port description
    • Elog – refactor, add debug info
    • I2C – add generic driver,
    • SPI – Add new chip support, major refactoring, don’t assume SPI flash boot device
  • Lib (33 commits)
    • Add real-time-clock functions
    • Add RW boot device construct
    • reg_script updates: add to bootblock, add xor support, add display support
    • Timestamp fixes & updates
  • Vendorcode
    • AMD (14 commits) – Cleanup, add libagesa.a builds, remove unused code.
    • Google (22 commits) – VBoot2 updates and cleanup
    • Intel (86 commits) – Add Intel FSP 2.0, update Broadwell DE support
  • Payloads (37 commits)
    • Subpayload support got extend and is enabled by default.
    • nvramcui: refactor, update build
    • SeaBIOS: Update stable version to 1.9.3, add bootorder file
    • iPXE: Update stable version to the last commit of July 2016
    • Fix broken linux boot sequence

Mainboard changes

Added 13 mainboards, plus a few mainboard variants not included here:

  • ADI RCC-DFF networking board (adi/rcc-dff) – intel/rangeley SoC
  • AMD Evaluation Board DB-FT3B-LC (amd/db-ft3b-lc) – amd/00730F01 (Family 16h Models 30h-3Fh (Mullins)) CPU
  • AMD f2950 / TONK 1201/2 Board (amd/f2950) – amd/geode_lx CPU
  • Apple iMAC 5.2 (apple/imac52) – intel/i945 CPU
  • Unibap Development Kit ODE E21XX – amd/00730F01 (Family 16h Models 30h-3Fh (Mullins)) CPU
  • elmex/pcm205400 – amd/Family_14 CPU
  • elmex/pcm205401 – amd/Family_14 CPU
  • Lenovo N21 chromebook (google/enguarde) – intel/baytrail SoC
  • google/gale – Qualcomm IPQ40XX SoC
  • AOpen Chromebox (google/ninja) – intel/baytrail SoC
  • google/reef – intel/apollolake SoC
  • Acer Chromebox CXI2 (google/rikku) – intel/Broadwell SoC
  • google/rotor – marvell/MVMAP2315 SoC

Removed 5 mainboards:

These were all development boards not available to the public.

  • google/bolt – intel/haswell – removed in commit 139314b
  • google/rush – nvidia/tegra132 – removed in commit e67cd9e
  • google/rush_ryu – nvidia/tegra132 – removed in commit 0c63415
  • google/slippy – intel/haswell – removed in commit bc24b85
  • intel/amenia – intel/apollolake – removed in commit c2586db

Existing boards with significant updates

  • asus/kgpe-d16 – amd/socket_G34 – Add TPM support, enable secondary serial port
  • emulation/spike-riscv: RISC-V -clean up, use generic bootblock,  look for CBFS in RAM, reimplement SBI
  • google/gru – rockchip/RK3399 SoC (76 commits) – Board bringup
  • google/oak – mediatek/mt8173 SoC- Add Elm variant, update memory, configure display, initialize touchscreen gpio
  • intel/galilleo- intel/quark SoC (14 commits) – Board bringup, add galileo gen1 support, switch to FSP2.0
  • intel/minnowmax – intel/fsp_baytrail SoC – Enable all PCIe ports, Program GPIO for power LED
  • lenovo/x60 – intel/socket_mPGA478 – init GPIOs before dock check, add hda verb table
  • siemens/mc_bdx1 – intel/fsp_broadwell_de SoC – Add external RTC, Set up MAC addresses, Update IRQs
  • siemens/mc_tcu3 – intel/fsp_baytrail SoC – cleanup & LCD panel updates

Changes in chips

Moved 3 northbridge/southbridge pairs to soc:

  • dmp/vortex86ex
  • intel/sch
  • rdc/r8610

Added 2 socs:

  • marvell/mvmap2315 (12 commits)
  • qualcomm/ipq40xx (22 commits)

Removed 1 soc:

  • nvidia/tegra132 – removed in commit 9ba0699

Added 2 sios:

  • nuvoton/nct6776
  • nuvoton/nct6791d

Existing chip areas with many changes

  • ARM (34 commits)
    • Add armv7-r configuration
    • rockchip/rk3399 (73 commits) – Bringup, memory updates
  • RISC-V (40 commits)
    • Improve and refactor trap handling
  • X86 (225 commits)
    • ACPI (40 commits) Add support for writing various entries and descriptor types, Add common definitions, Use ‘GOOG’ id for coreboot table
    • amd/mct_ddr3 northbridge: Support non-ECC DIMMs, Update SMBIOS, various fixes
    • arch/x86: many postcar stage updates, add common ACPI definitions, Support “weak” BIST and timestamp save routines
    • intel/apollolake SoC (211 commits) – Chip bringup, Update bootblock
    • intel/common: ACPI updates, Add smihandler, LPSS I2C driver, and  IGD OpRegion support
    • intel/fsp_broadwell_de: IRQ fixes, SPI message fixes, Add DMAR table to ACPI
    • intel/gm45 northbridge: Fix text mode init, enable vesa framebuffer, use VGA if connected
    • intel/i945 northbridge: add native VGA init, Update divisor calculations
    • intel/quark SoC (62 commits) – Chip bringup, add Fsp2.0 support, updates for serial console
    • intel/skylake CPU (61 commits) – Finished Skylake bringup, start updating for Kabylake FSP
    • intel/x4x northbridge (13 commits) – Memory & Graphics updates


Updated 4 submodules

  • 3rdparty/blobs (6 commits)
  • 3rdparty/arm-trusted-firmware (425 commits)
  • 3rdparty/vboot (61 commits)
  • 3rdparty/chromeec/ (676 commits)

Tested boards

The following boards were tested for this release:

  • asrock/e350m1              4.4-1890
  • asus/kfsn4-dre               4.4-1698 / 4.5-17
  • asus/kgpe-d16                4.4-1802 / 4.5-17
  • emulation/qemu-q35   4.4-1698 / 4.5-8
  • gigabyte/ga-b75m-d3v 4.4-1757
  • google/peppy                 4.4-1882
  • lenovo/g505s                 4.4-1739
  • lenovo/x201                   4.4-1886
  • lenovo/x220                   4.4-1746 / 4.5-17

coreboot statistics

Total Commits: 1889
Average Commits per day: 10.92
Total authors: 119
New authors: 47
Total Reviewers: 67
Total Submitters: 19
Total lines added: 164950
Total lines removed: -182737
Total difference: -17787

Announcing coreboot 4.4

We are happy to announce the release of coreboot 4.4.  This is our fourth quarterly release.  Since the last release, we’ve had 850 commits by 90 authors adding 59000 lines to the codebase.

The release tarballs are available at
There is a 4.4 tag and branch in the git repository.

Log of commit 3141eac900 to commit 588ccaa9a7

Major areas that received significant changes in for this release:

  • Build system (30 commits) – Add postcar stage, ‘timeless’ builds, extend site-local, test toolchain by version string, update dependencies, catch ACPI errors, l add additional macros.
  • Toolchain updates (40+ patches) – Update IASL to v20160318 , LLVM to v3.7.1, add GNU make, add nds32le GCC compiler
  • Lint tools (30 patches) – Update existing lint utilities, add lint tests for executable bit, make sure site-local isn’t committed, add test to break all lint tests.
  • Payloads (60 commits) – Fixes for libpayload, coreinfo and nvramcui, add new payloads, see below.
  • Maintainers file – (8 patches) – continue adding maintainers for various areas.
  • Documentation for adding Intel FSP-based platforms (20 commits)


Added 9 mainboards

  • asus/kcma-d8
  • emulation/qemu-power8
  • google/auron_paine
  • google/gru
  • intel/amenia
  • intel/apollolake_rvp
  • intel/camelbackmountain_fsp
  • intel/galileo
  • lenovo/t420

Existing boards with significant updates

  • asus/kgpe-d16
  • google/oak
  • google/chell
  • intel/kunimitsu

Changes in chips

Added 1 new architecture

  • power8

Added 1 processor

  • qemu-power8

Added 5 socs

  • intel/apollolake
  • intel/fsp_broadwell_de
  • intel/quark
  • marvell/armada38x
  • rockchip/rk3399

Existing chip areas with many changes

  • cpuamd/mct_ddr3
  • drivers/intel/fsp2_0
  • northbridge/intel/sandybridge/raminit
  • soc/intel/apollolake
  • soc/intel/fsp_baytrail
  • soc/intel/skylake
  • soc/mediatek/mt8173

Added 1 new vendorcode directory

  • siemens


Added 1 submodule

  • chromeec

Updated 3 submodules

  • 3rdparty/arm-trusted-firmware (329 commits)
  • 3rdparty/vboot (28 commits)
  • util/nvidia/cbootimage (13 commits)


Added 4 payloads

  • depthcharge: For ChromeOS verified boot
  • iPXE: For network booting
  • Memtest86+: Updated with fixes for correctly testing coreboot with payloads
  • U-Boot (Experimental): Alternate payload for booting an OS

Added 6 utilities

  • archive – Concatenates files into a single blob with an indexed header
  • chromeos – Download and extract blobs from a ChromeOS image
  • futility – vboot Firmware utility
  • intelmetool – Shows information about the Intel ME on a platform.
  • marvell/doimage_mv – No usage notes
  • post – Simple utility to test post cards

coreboot statistics

  • Total Commits:    850
  • Total authors:        90
  • New authors:         28
  • Total Reviewers:   40
  • Total Submitters:  17
  • Total lines added:       74054
  • Total lines removed: -15056
  • Total difference:          58998

coreboot changelog March 2 – March 15

This changelog covers 187 commits in the two week period between March 2, 2016 and March 15, 2016. (c77e0419 – 80547369)

Once again this time, we had many changes in the payloads area. We added a memtest86+ git repository, and set it up as a secondary payload within the coreboot build process. SeaBIOS updated the stable version from 1.9.0 to 1.9.1 and has a new option to build from any specified commit instead of just master or stable branches. Google’s depthcharge payload was added for ChromeOS builds, and the coreinfo payload started getting some updates – removing obsolete pieces, fixing the makefile, and correcting issues with cbfs.

The MediaTek MT8173 ARM based SOC and the Google OAK board using it received a significant number of patches, adding trusted firmware support, and initialization routines for memory, USB, audio, TPM, GPIOs, I2c and RTC.

Several other groups of patches were to perform cleanup for various chipsets. One series unified and fixed up the UDELAY settings, many of which were incorrectly specifying TSC delays which weren’t supported by those platforms. Other sets removed code #includes of C files, merged the MRC cache implementations into a single common version, and combined Sandybridge & Ivybridge LVDS implementations. The FSP version of Intel’s Bay Trail was updated to mirror the non-FSP implementation, enabling LPE and LPSS in ACPI mode. The plan with Bay Trail is to make the two versions as similar as possible, then work to combine the directories and use common code for both.

Intel has started adding support for their Xeon D (Broadwell DE) processor. So far only the vendorcode has been merged.  The coreboot code is another 4700 lines of chipset code and 800 lines of mainboard code, so that’s taking some time to get reviewed.

The patches bringing up the Quark and Apollo Lake Intel chips continued, with Quark getting minor updates and Apollo Lake continuing to add core functionality like memory init and the various calls into the FSP.

Additional work was done on Skylake as well, updating the FSP parameter table, adding a Voltage Regulator mailbox command, and adding clock gating for the 8254 timer.

Utilities only got a few changes this time. The cbmem utility got a fix a regression and correctly scale the timestamp values and an option to change the SPI ROM chip sizes was added to ifdtool. Cbfstool got a couple of fixes as well, making sure the structure sizes are the same whether compiled for 32-bit or 64 bit platforms, and zeroing out unused Linux parameters.

AMD’s native memory initialization got some more cleanup and several fixes, restoring DQS delay values on a failed loop, and making sure that both read and write training pass before proceeding to the next training phase instead of continuing when either one passed.

SMBIOS changes included a patch to add SMBIOS type 17 (Memory) fields to the Sandy Bridge / Ivy Bridge platforms, and another patch to fix the length calculated for those fields for every platform. A third patch added the names of several different DIMM vendors.

The X86 bootblock renamed several symbols for clarification, removed some unused code, and marked the reset vector as executable so it would show up in objdump.

We had a slew of patches from new authors merged in the past two weeks. Welcome to all new authors and thank you to everyone.

Antonello Dettori had 3 patches merged, allowing SeaBIOS to be build from any revision, and cleaning up early serial on the roda rk9 and amd thatcher platforms.
Bayi Cheng wrote a patch adding NOR flash DMA read routines for the Mediatek MT8173.
Georg Wicherski updated and added Google’s auron paine board.
Huki Huang modified the ChromeOS wifi regulatory domain to use the region key from VPD.
Jan Tatje updated the Intel Firmware Descriptor tool (iftdool) to allow the SPI rom sizes to be updated.
Jitao Shi added the parade ps8640 MIPI-to-eDP video format converter driver.
Jonathan Neuschäfer had an astounding 7 patches merged in his first couple of weeks submitting to coreboot. He fixed a syntax error in buildgcc, and updating several areas in coreinfo.
Jun Gao did I2C work on Mediatek MT8173 and on Google’s Oak board,
Lance Zhao had a pair of patches for Intel’s Apollo Lake reference board, setting up the devicetree, and adding memory training configuration.
Medha Garima added runtime SD card detection to Intel’s Kunimitsu board.
Milton Chiang had a patch updating the infracfg register map for the Mediatek MT8173.
Peter Kao wrote a pair of patches adding DRAM initialization to the Mediatek MT8173 and Google’s Oak board.
PH Hsu set up 4GB mode on Mediatek MT8173 and Google’s Oak board.

coreboot statistics

- Total commits: 187
- Total authors: 44
- New authors: 13
- Total lines added: 15724
- Total lines removed: -1750
- Total difference: 13974

Added 1 mainboards: google/auron_paine
Added 1 new driver: parade/ps864C

=== Top Authors - Number of commits ===
Martin Roth                  27 (14.439%)
Stefan Reinauer              24 (12.834%)
Andrey Petrov                18 (9.626%)
Aaron Durbin                 15 (8.021%)
Yidi Lin                      8 (4.278%)
Timothy Pearson               8 (4.278%)
Jonathan Neuschäfer           7 (3.743%)
Patrick Rudolph               7 (3.743%)
Leroy P Leahy                 6 (3.209%)
Alexander Couzens             5 (2.674%)
Duncan Laurie                 5 (2.674%)
Total Authors: 44

=== Top Authors - Lines added ===
Peter Kao                  3750 (23.849%)
Andrey Petrov              2536 (16.128%)
York Yang                  2509 (15.956%)
Georg Wicherski            2214 (14.080%)
Alexandru Gagniuc           409 (2.601%)
Ben Gardner                 406 (2.582%)
Leroy P Leahy               384 (2.442%)
Daisuke Nojiri              373 (2.372%)
Bayi Cheng                  314 (1.997%)
Martin Roth                 256 (1.628%)

=== Top Authors - Lines removed ===
Alexander Couzens           309 (17.657%)
Leroy P Leahy               255 (14.571%)
Stefan Reinauer             207 (11.829%)
Aaron Durbin                162 (9.257%)
Jonathan Neuschäfer         156 (8.914%)
Timothy Pearson             127 (7.257%)
Julius Werner                93 (5.314%)
Zheng Bao                    87 (4.971%)
Martin Roth                  66 (3.771%)
Andrey Petrov                58 (3.314%)

=== Top Reviewers - Number of patches reviewed ===
Martin Roth                  82 (43.850%)
Stefan Reinauer              62 (33.155%)
Paul Menzel                  45 (24.064%)
Aaron Durbin                 28 (14.973%)
Andrey Petrov                13 (6.952%)
Patrick Georgi               12 (6.417%)
Furquan Shaikh                6 (3.209%)
Timothy Pearson               4 (2.139%)
Ronald G. Minnich             4 (2.139%)
Alexander Couzens             4 (2.139%)
Total Reviewers: 22

=== Submitters - Number of patches submitted ===
Martin Roth                  85 (45.455%)
Patrick Georgi               47 (25.134%)
Aaron Durbin                 24 (12.834%)
Stefan Reinauer              20 (10.695%)
Vladimir Serbinenko           4 (2.139%)
Werner Zeh                    2 (1.070%)
Timothy Pearson               2 (1.070%)
Zheng Bao                     1 (0.535%)
Leroy P Leahy                 1 (0.535%)
Ronald G. Minnich             1 (0.535%)
Total Submitters: 10

GSoC 2016

The coreboot project is proud to announce that it has been selected as one of the 2016 Google Summer of Code (GSoC) mentor organizations. GSoC is a program designed to encourage university students age 18 and older to participate in open source projects. This is done by paying students to partner with experienced mentors from the selected open source projects to work on a specific project chosen by the student. This helps the mentor organization by encouraging participation and getting tasks done while helping the student get involved in open source, add projects to their resume, and learn from experienced open-source participants.

Student applications begin next Monday, March 14th, 2016, and close on Friday, March 25th.  Accepted student projects will be announced on April 22nd. Any students who are interested in applying for a coreboot, flashrom, or SerialICE GSoC project should look at the GSoC student terms page, and at both coreboot’s GSoC page and the coreboot / Flashrom / SerialICE projects page.  Projects are not limited to what is currently listed here. Students typically select from these, but if you have other ideas of projects in our space, we’d love to hear about them.

As noted above, coreboot acts as an umbrella organization for other firmware related open-source projects, currently supporting Flashrom and SerialICE. If there are other firmware related projects who would like to be included under the coreboot project for GSoC, please contact the project administrators, Patrick Georgi or Martin Roth.

Finally, if you are a developer who would like to volunteer as a mentor, please contact us. First year volunteers will generally be teamed up with experienced mentors, so don’t worry about not having previous experience. If you’re interested, you can read more about mentoring expectations in the GSoC mentoring Guide.

coreboot changelog Feb 17 – March 1

This changelog covers 105 commits in the two week period between February 17, 2016 and March 1, 2016. (6a622311 – 163506a8)

We’ve entered a lower volume period for patches being submitted, so for a while, blog posts will be every two weeks instead of every week. Once we get above 100 patches a week, blog posts will be weekly again.

Payloads got some attention during this period, adding a way to include additional modules into the GRUB2 build. An option was added to build and include coreinfo as a ‘secondary’ payload, allowing it to be run from another payload. We also added U-Boot as a coreboot payload. This is currently still just in development, and needs additional work before it will act as a generic payload for all platforms.

We added LZ4 compression to the build with runtime decompression for cbfs. LZ4’s speed should be roughly the same as LZMA, trading a smaller compressed size for slightly slower decompressoin. LZ4’s main advantage is that it requires much less memory to do the decompression, allowing for compression of stages that couldn’t previously be compressed.

The suite of board-status scripts got several updates, fixing timestamp handling for the sanitized path names, handling when the script is run as super-user in a better way, and adding a script that will set up a Ubuntu Live-image to allow users to more easily run the board-status script.

In the build tools and utilities, we had some fixes for the toolchain builder, updating the GDB builds for x86_64 and MIPS. A couple of scripts were also added. One utility downloads and extracts binary blobs from Chrome OS recovery images, and the other new script allow easier testing of POST cards.

Intel based boards and chipsets received a large percentage of the patches for the past two weeks:

The Galileo board and Quark chip had several pieces new added, along with additional documentation for those changes. Major pieces done were to set up the basic registers, in the ACPI FADT, setting up the memory map, and enabling the UART.

We received the final set of patches to finish out the changes combining many of the the Intel GPIO initialization routines into a single common set of functions. The autoport script was updated to use the common GPIO functions.

Sandy Bridge / Ivy Bridge memory initialization also continued to receive updates, adding support for XMP profiles in the SPD, updating logging, and fixing some bugs.

Intel’s Skylake chipset and boards were updated to enable Hardware P-state control (HWP) based on Intel’s Speed Shift Technology (SST). Another change to Skylake platforms increased stolen memory for graphics to 64MB.

Intel Bay Trail got a couple of updates, adding a fix for issues with displayport on the FSP version, and adding IOSF access support to the reg_script module.

Intel Apollo Lake had several more foundational pieces added to the codebase. Many more patches for Apollo Lake are expected in the next couple of weeks.

On the non-X86 side, the instructions for running the Arm7 Qemu board were updated, and the memory map was corrected.

RISC-V got a couple of patches, adding additional debugging, and fixing some inline asm code.
The coreboot project would like to recognize another pair of developers who have hit major milestones in the past two weeks:

Lee Leahy just reached his 100th commit merged into Lee is a developer with Intel who has been working on coreboot for about a year and a half. He has worked on many of the recent intel chipsets, and is currently adding support and documentation for the Intel Galileo board and Quark chips in a way that each step of the process can be tested and verified. While this takes significantly more effort than the typical method of porting, it should result in a better platform.

Tobias Diedrich has just had his 50th patch merged.  Tobias has been contributing patches to coreboot for over five years, and his patches have spanned a number of boards and chipsets.

Finally, please welcome our newest authors:
Andrew Waterman contributed the pair of RISC-V patches.
Joe Pillow added the Chrome OS recovery image script.

coreboot statistics

- Total commits: 105
- Total authors: 25
- Total lines added: 13396
- Total lines removed: -3127
- Total difference: 10269

Added 1 mainboard: emulation/qemu-power8
Added 1 processor: qemu-power8

Submodule updates:
- 3rdparty/arm-trusted-firmware (329 commits)
- 3rdparty/vboot (2 commits)

=== Top Authors - Number of commits ===
Leroy P Leahy                20 (19.048%)
Aaron Durbin                 11 (10.476%)
Patrick Rudolph               8 (7.619%)
Patrick Georgi                8 (7.619%)
Martin Roth                   8 (7.619%)
Stefan Reinauer               5 (4.762%)
Vladimir Serbinenko           5 (4.762%)
Denis 'GNUtoo' Carikli        4 (3.810%)
Julius Werner                 4 (3.810%)
Werner Zeh                    4 (3.810%)
Duncan Laurie                 4 (3.810%)
Ronald G. Minnich             4 (3.810%)
Total Authors: 25

=== Top Authors - Lines added ===
Julius Werner              7602 (56.748%)
Leroy P Leahy              1255 (9.368%)
Ronald G. Minnich          1097 (8.189%)
Stefan Reinauer             990 (7.390%)
Werner Zeh                  479 (3.576%)
Patrick Rudolph             406 (3.031%)
Damien Zammit               336 (2.508%)
Martin Roth                 293 (2.187%)
Aaron Durbin                232 (1.732%)
Joseph Pillow               218 (1.627%)

=== Top Authors - Lines removed ===
Stefan Reinauer            1662 (53.150%)
Patrick Rudolph             936 (29.933%)
Julius Werner               154 (4.925%)
Aaron Durbin                128 (4.093%)
Leroy P Leahy                93 (2.974%)
Damien Zammit                21 (0.672%)
Patrick Georgi               20 (0.640%)
Vladimir Serbinenko          17 (0.544%)
Tobias Diedrich              15 (0.480%)
David Hendricks              13 (0.416%)

=== Top Reviewers - Number of patches reviewed ===
Martin Roth                  43 (40.952%)
Stefan Reinauer              33 (31.429%)
Paul Menzel                  30 (28.571%)
Aaron Durbin                 13 (12.381%)
Andrey Petrov                 8 (7.619%)
Furquan Shaikh                8 (7.619%)
Patrick Georgi                6 (5.714%)
Ronald G. Minnich             5 (4.762%)
Timothy Pearson               4 (3.810%)
Patrick Rudolph               3 (2.857%)
Total Reviewers: 18

=== Top Submitters - Number of patches submitted ===
Martin Roth                  40 (38.095%)
Leroy P Leahy                18 (17.143%)
Stefan Reinauer              13 (12.381%)
Patrick Georgi                8 (7.619%)
Aaron Durbin                  8 (7.619%)
Vladimir Serbinenko           5 (4.762%)
Ronald G. Minnich             4 (3.810%)
Julius Werner                 4 (3.810%)
Werner Zeh                    3 (2.857%)
Total Submitters: 11

coreboot changelog Feb 10 – Feb 16

This changelog covers 77 commits in the week between February 10, 2016 and February 16, 2016. (318ef96a – 0188b139)

Many of the big changes this week surrounded native initialization of the Sandy Bridge/Ivy Bridge platforms. We got patches to change platforms which had been previously based on Intel’s MRC blob to build with either the MRC or coreboot’s native memory initialization. We also got patches combining the Intel GPIO initialization for various chipsets into a single common set of functions.

Continuing the series from the past several weeks, we merged patches for the Intel Apollo Lake, Skylake, and Quark platforms. Apollo Lake got a skeleton for its initial mainboard, and added code to support GPIO init. Quark added FSP initialization and MTRR support. The more mature Skylake SoC received some minor fixes for graphics and to finalize SMM inside coreboot.

Another of the Intel FSP platforms, the FSP version of the Intel Bay Trail codebase was updated to support version 5 of the Bay Trail FSP, which should be released to the Intel website shortly.

On the ARM side, we got several small fixes, and a patch to verify consistency of the page table descriptors. This sounds like it will help prevent ‘interesting’ debug sessions due to conflicting memory types for the same memory area.

The build system and toolchain received fixes for issues downloading git submodules, for the gitconfig make target, and for building under paths that have an ‘@’ character in their name. A couple of changes were added to make Kconfig’s strict mode slightly less strict and more user friendly.

Two new lint tools were added this week, one to make sure that the site-local directory doesn’t get pushed and committed, and another that checks over the Kconfig files for various issues.

Other changes this week included a change to allow bootblock code to use CAR_GLOBAL variables, and continued work updating and adding license headers throughout the coreboot codebase.

Finally, I’d like to recognize two contributors this week:

Damien Zammit (damo22) reached his 50th commit merged into coreboot last week. His contributions have included the addition of two complete platforms, the Intel D510MO board with the Intel Pineview Atom processor, and the Gigabyte GA-G41M-ES2L board with the Intel x4x northbridge and Intel i82801gx southbridge. Damien joined coreboot in July of 2013, but has recently become very active.

Vladimir Serbinenko (phcoder) just broke 550 patches merged with his work moving Sandy Bridge/Ivy Bridge MRC platforms to native init mentioned earlier. Vladimir joined coreboot just under 3 years ago, and has been a fantastic contributor to the community.

Thanks to both of you, and to all the rest of the coreboot contributors.

coreboot statistics

- Total commits: 77
- Total authors: 16
- Total lines added: 6494
- Total lines removed: -1569
- Total difference: 4925

Added 1 mainboard: intel/apollolake_rvp

=== Top Authors - Number of commits ===
Patrick Georgi               12 (15.584%)
Vladimir Serbinenko          12 (15.584%)
Aaron Durbin                  9 (11.688%)
Julius Werner                 7 (9.091%)
Andrey Petrov                 6 (7.792%)
Duncan Laurie                 5 (6.494%)
Martin Roth                   5 (6.494%)
Leroy P Leahy                 4 (5.195%)
Alexandru Gagniuc             3 (3.896%)
Patrick Rudolph               3 (3.896%)
Yves Roth                     3 (3.896%)
Stefan Reinauer               3 (3.896%)

=== Top Authors - Lines added ===
Ruilin Hao                 2528 (38.928%)
Andrey Petrov               817 (12.581%)
Vladimir Serbinenko         681 (10.487%)
Yves Roth                   678 (10.440%)
Leroy P Leahy               451 (6.945%)
Patrick Rudolph             355 (5.467%)
Alexandru Gagniuc           242 (3.727%)
Aaron Durbin                213 (3.280%)
Patrick Georgi              194 (2.987%)
Julius Werner               131 (2.017%)

=== Top Authors - Lines removed ===
Vladimir Serbinenko         892 (56.851%)
Aaron Durbin                247 (15.743%)
Julius Werner               244 (15.551%)
Patrick Georgi               68 (4.334%)
Yves Roth                    64 (4.079%)
Martin Roth                  13 (0.829%)
Duncan Laurie                12 (0.765%)
Patrick Rudolph              11 (0.701%)
Andrey Petrov                 7 (0.446%)
Ruilin Hao                    4 (0.255%)

=== Top Reviewers - Number of patches reviewed ===
Martin Roth                  31 (40.260%)
Aaron Durbin                 16 (20.779%)
Patrick Georgi               13 (16.883%)
Paul Menzel                  13 (16.883%)
Alexandru Gagniuc            12 (15.584%)
Stefan Reinauer              11 (14.286%)
FEI WANG                      3 (3.896%)
York Yang                     2 (2.597%)
Andrey Petrov                 2 (2.597%)
Total Reviewers: 15

=== Submitters - Number of patches submitted ===
Martin Roth                  25 (32.468%)
Aaron Durbin                 19 (24.675%)
Patrick Georgi               15 (19.481%)
Vladimir Serbinenko           6 (7.792%)
Stefan Reinauer               6 (7.792%)
Julius Werner                 5 (6.494%)
Ronald G. Minnich             1 (1.299%)
Total Submitters: 7

coreboot changelog Feb 3 – Feb 9

This changelog covers 107 commits in the week between February 3, 2016 and February 9, 2016. (2cc2ff6f – c285b30b)

This week, it looks like the biggest set of changes were the changes directly supporting chrome verified boot, adding options for the GBB flags and supporting VBNV (vboot non-volatile storage) in cmos, flash, and the EC. The verified boot (vboot) submodule included by coreboot was also updated, bringing in another 26 patches. These changes included a variety of work committed to the chromium vboot repo over the past several months. Another submodule was added this week to bring the Chrome EC codebase into the coreboot tree. There were several additional commits to update the build to use the new submodule.

The Intel Skylake and associated boards continued to get updates including more GPIO fixes, disabling the PM timer in ACPI, and unconditionally setting up the BAR for the SPI controller.

Intel continued adding documentation in the Documentation/Intel directory. This is mostly targeting the newly added Galileo mainboard, the newly added Quark X1000 Soc, and version 1.1 of the Intel FSP.

The AMD Family 10h / Family 15h directory and mainboard got some more patches, updating the RDIMM memory training code to work around some failures. The other main feature added was a CMOS option to enable/disable core boost.

There were a number of ACPI ASL changes this week. Several were bugfixes, some were to get rid of unused variables causing warning, and others worked around different warnings generated by new versions of the IASL ACPI compiler. These will help the effort to upgrade the IASL ACPI compiler to the latest version.

The native memory initialization code for the Intel Sandybridge/Ivybridge platforms had a fix for using two DIMMs per channel, and there were a few changes working towards switching the MRC based Sandybridge/Ivybridge implementations over to using native graphics and memory initialization. The goal is that the boards that currently use the Intel MRC should be able to build with either path. More of these changes will be merged in the coming weeks.

The toolchain builder, buildgcc, had several changes to clean up and reorganize the makefiles, and to add a toolchain build for the nds32le architecture in support of the chrome EC builds.

coreboot’s site-local directory was extended to use a Kconfig file and adds a make target which gets run at the end of the rest of the build. Documentation on how to use this should be completed and released next week.

Miscellaneous other fixes include a new lint test ensuring assembly is in AT&T syntax, an update to the QT version for the ‘xconfig’ Kconfig front end, adding PS/2 Aux presence detect to the nuvoton nct5572d SuperIO, and adding a new ARM SoC, Marvell’s Armada 38x.

Thank you to everyone who contributes to the coreboot community.

New issues that we saw this week

– The toolchain build seems to be broken for some people as of commit 8e68aff51 – “buildgcc: enable multilib for gcc”
– There were issues with make gitconfig on a newly cloned repo caused by commit ec0b586 – “3rdparty/chromeec: Add Chrome EC firmware sources”.
– Commit ec0b586 – “3rdparty/chromeec: Add Chrome EC firmware sources” also causes issues pulling down the blobs submodule.

New bugs filed this week

– board-status allows invalid uploads
– Windows doesn’t like ToString() calls in ACPI
– [Haswell/Broadwell] LPC power optimizer RCBA instructions break eDP display with Intel VBIOS
– cbmem utility fails on newer linux kernels “Failed to mmap /dev/mem: Resource temporarily unavailable”
– Provide and use enums for SerialIoI2cVoltage

coreboot statistics for the past week

- Total commits: 107
- New authors: 3
- Total authors: 24
- Total reviewers: 14
- Total lines added: 13759
- Total lines removed: -1974
- Total difference: 11785

Added 2 mainboards: asus/kcma-d8 & intel/galileo
Added 1 mainboard variant: lenovo/X220i
Added 2 SoCs: intel/quark & marvell/armada38x

=== Top Authors - Number of commits ===
Leroy P Leahy                15 (14.019%)
Patrick Georgi               15 (14.019%)
Aaron Durbin                 14 (13.084%)
Vladimir Serbinenko          10 (9.346%)
Timothy Pearson               8 (7.477%)
Duncan Laurie                 7 (6.542%)
Martin Roth                   6 (5.607%)
Stefan Reinauer               6 (5.607%)
Ruilin Hao                    5 (4.673%)
Total Authors: 25

=== Top Authors - Lines added ===
Timothy Pearson            3956 (28.752%)
Ruilin Hao                 2964 (21.542%)
Leroy P Leahy              2780 (20.205%)
Duncan Laurie              1091 (7.929%)
Zheng Bao                   463 (3.365%)
Dhaval Sharma               450 (3.271%)
Patrick Georgi              397 (2.885%)
Aaron Durbin                397 (2.885%)
Lee Leahy                   346 (2.515%)
Edward O'Callaghan          236 (1.715%)

=== Top Authors - Lines removed ===
Zheng Bao                   426 (21.581%)
Edward O'Callaghan          393 (19.909%)
Duncan Laurie               323 (16.363%)
Timothy Pearson             223 (11.297%)
Vladimir Serbinenko         108 (5.471%)
Stefan Reinauer             106 (5.370%)
Aaron Durbin                 84 (4.255%)
Pratik Prajapati             79 (4.002%)
Martin Roth                  62 (3.141%)
Patrick Georgi               49 (2.482%)

=== Top Reviewers - Number of patches reviewed ===
Martin Roth                  55 (51.402%)
Stefan Reinauer              44 (41.121%)
Aaron Durbin                  8 (7.477%)
FEI WANG                      6 (5.607%)
Patrick Georgi                6 (5.607%)
Paul Menzel                   5 (4.673%)
Timothy Pearson               2 (1.869%)
Leroy P Leahy                 2 (1.869%)
Alexander Couzens             2 (1.869%)
Felix Held                    2 (1.869%)
Total Reviewers: 14

=== Submitters - Number of patches submitted ===
Patrick Georgi               44 (41.121%)
Martin Roth                  37 (34.579%)
Stefan Reinauer              13 (12.150%)
Leroy P Leahy                11 (10.280%)
Vladimir Serbinenko           2 (1.869%)
Total Submitters: 5

coreboot changelog Jan 27 – Feb 2

This changelog covers 131 commits in the week between January 27, 2016 and February 2, 2016. (dd4b66e2 – 95909924)

The biggest news of the past week was getting the 4.3 release done. The 4.4 release should come towards the end of April.

Of particular note to anyone submitting patches, we added 2 new code checkers this week, one to verify that the executable bit isn’t set on source files, and one to verify that the standard coreboot license header is used on files using the GPL 2 or 2+ licenses. These checks will be run automatically when you commit code if you have the git commit hook in place, and will also be run on the build server.

coreboot again had numerous patches surrounding the build system, tools, and utilities. The flood of cbfstool related patches finally slowed a bit, but we still had some cleanup, both in the tool and in the cbfs sections of the Makefiles. In the toolchain area, we updated LLVM to version 3.7.1, and added GNU Make to the toolchain. The addition of make was to address some upcoming patches that needed the newer version, as well as to support platforms that don’t install GNU make by default. The kconfig_lint tool had various updates to get rid of warnings that we don’t care about, to add documentation, and to add a couple of additional checks. Next week will see a few more fixes, and it will be put in place as a stable lint tool.

We had significant updates to a number of mainboards and the related chipsets in the past week as well. Intel had a large number of changes for their Braswell SoC and its reference board, Strago, merged this week. These included fixes for GPIOs, clocks, SD cards, and thermal support, as well as FSP integration updates. The Asus kgpe-d16 mainboard, along with the AMD Fam10h-Fam15h processor directory and the SB700 soutbridge had numerous patches to improve stability, fix IRQ routing and APIC identification, and improve ACPI. The winbond w83667hg-a was added to the coreboot codebase for the board as well. The Intel d510mo board had some improvements related to native graphics initialization, GPIOs and ACPI. The gigabyte ga-g41m-es2l and the Intel x4x northbridge code had some general cleanup and improvements to cbmem and memory initialization. We also saw the introduction of the initial framework for the new Intel Apollo Lake SoC. We’ll be seeing many more patches related to Apollo Lake in the coming weeks.

Other changes of note included code to initialize the PS/2 aux port, a way to access memory address 0 without GCC “optimizing” it into a crash, and the addition of some documentation from Intel about developing new FSP based boards and chipsets. Finally, the Intel sklrvp Skylake reference board was dropped in favor of using the kunimitsu board.

coreboot statistics for the past week

- Total commits: 131
- New authors: 8
- Total authors: 30
- Total lines added: 3833
- Total lines removed: -3652
- Delta: 181

=== Top Authors - Number of commits ===
Timothy Pearson              22 (16.794%)
Martin Roth                  21 (16.031%)
Patrick Georgi               15 (11.450%)
Damien Zammit                13 (9.924%)
Hannah Williams              12 (9.160%)
Leroy P Leahy                 5 (3.817%)
Stefan Reinauer               5 (3.817%)
Divagar Mohandass             4 (3.053%)
Vladimir Serbinenko           3 (2.290%)
Alexandru Gagniuc             3 (2.290%)
Total Authors: 31

=== Top Authors - Lines added ===
Damien Zammit               725 (18.915%)
Timothy Pearson             701 (18.289%)
Leroy P Leahy               646 (16.854%)
Subrata Banik               427 (11.140%)
Martin Roth                 262 (6.835%)
Aaron Durbin                204 (5.322%)
Patrick Georgi              179 (4.670%)
Alexandru Gagniuc           140 (3.652%)
shkim                       107 (2.792%)
Nico Huber                   91 (2.374%)

=== Top Authors - Lines removed ===
Martin Roth                1688 (46.221%)
Hannah Williams             661 (18.100%)
Divagar Mohandass           315 (8.625%)
Damien Zammit               307 (8.406%)
Timothy Pearson             212 (5.805%)
Patrick Georgi              104 (2.848%)
Nico Huber                  102 (2.793%)
Leroy P Leahy                95 (2.601%)
Stefan Reinauer              43 (1.177%)
Lee Leahy                    23 (0.630%)

=== Top Reviewers - Number of patches reviewed ===
Martin Roth                  71 (54.198%)
Stefan Reinauer              20 (15.267%)
Patrick Georgi               18 (13.740%)
Paul Menzel                  16 (12.214%)
Alexandru Gagniuc            14 (10.687%)
Aaron Durbin                 10 (7.634%)
Felix Held                    8 (6.107%)
Timothy Pearson               7 (5.344%)
Nico Huber                    4 (3.053%)
Alexander Couzens             3 (2.290%)
Total Reviewers: 15

=== Top Submitters - Number of patches merged ===
Martin Roth                  94 (71.756%)
Patrick Georgi               15 (11.450%)
Stefan Reinauer               8 (6.107%)
Leroy P Leahy                 6 (4.580%)
Vladimir Serbinenko           3 (2.290%)
Nico Huber                    2 (1.527%)
Aaron Durbin                  2 (1.527%)
Werner Zeh                    1 (0.763%)
Total Submitters: 8