GSoC 2011: flashrom part 2 – SFDP

SFDP (Serial Flash Discoverable Parameters) is a JEDEC standard for querying the capabilities of serial flash chips. This allows software like flashrom to support chips without having all properties hard-coded beforehand. SFDP is structured in tables which are laid out in their own linear address space (independent from the “normal” range used to access the stored data). Starting at address 0x0 a mandatory header begins with a signature 0x50444653 (or ‘S’, ‘F’, ‘D’, ‘P’ in ASCII) followed by versioning data and the number of parameter headers. These headers are 64b long and have fields for versioning data, identification, length and offset where the real stuff i.e. the parameter table resides. There is one mandatory table and up to 255 can be added optionally. In the current version of the standard (2011-04) only the mandatory table is defined, but vendors are free (and quite encouraged by the standard) to add their customized tables and from the few data sheets i have seen mentioning SFDP the vendors do that (see below).

I spare you from the nasty details, but keep in mind that the mandatory table allows to retrieve the following properties:

• the total size of the device
• 4 (unified) block erasers (size of erase blocks and associated opcode)
• address mode (24b, 32b or both)
• status register write enable (none, WREN or EWSR)
• lots of fast read-related stuff (like modes supported and number of wait states/dummy cycles needed in each)

The good news is: this would be enough to allow flashrom to work with unknown (yet unreleased) chips without recompilation!

The even better news is: i have a patch for that 😉

The bad news: i am not sure if there exists any hardware that supports it yet.

History and current state

A similar preliminary white paper was published by Intel (i could not find a download for it though). The JEDEC standard refers to it in its “Legacy Compatibility” section at the end of the document: “Prior to the release of this document, Intel published SFDP guidelines with a four DWORD parameter table. The first four DWORDs of the JEDEC Parameter Table [referred to as the mandatory table above] are identical to the table in Intel’s guidelines.” This can be (and is in my patch) checked with the length field of the header.

If you currently search for “SFDP Serial Flash Discoverable Parameters” with google you will get 43 hits. Doh! But at least those hits are quite promising… mostly.

Besides references to the JEDEC document linked above, there are also a few data sheets that mention SFDP. Intel’s 6 Series data sheet describes it briefly without much relevance (i could name a number of other things which SHOULD be in there instead… ;)).

Winbond seems to marketing SFDP – it is not only used in (some) data sheets of the W25Q series (e.g. W25Q128BV) but also on their homepage and their flash selection guide.

Another data sheet that even includes a customized table is the one of EON/SSI’s EN25QH16. It notes supply voltage range and support for HOLD, deep power and OTP (one time programmable) among other things in a second table.

After digging around i have found a few remarkable details:

1. Generalplus has removed the entry of SFDP from one of their data sheets.
2. Spansion has copied the (whole?) data sheet of Winbond’s W25Q32BV literally into the preliminary data sheet of the S25FL032K.
3. Last year’s version (rev. E, 2010-07) of the data sheet of said W25Q32BV promised that:

Most Winbond SpiFlash Memories shipped after June 2010 (date code 1023 and beyond) support the SFDP feature as specified in the applicable datasheet.

Oh how was i excited! I have bought some of those in April!

Then Peter noted that there is an updated data sheet for that chip. From April. Stating:

Most Winbond SpiFlash Memories shipped after June 2011 (date code 1124 and beyond) support the SFDP feature as specified in the applicable datasheet.

I am not a big fan of memes, but this deserves one.

Conclusion

So all in all my work might not be useful right now, but at least i hope it will be integrated soon-ish and be of use later when SFDP is used in real world devices – after all the whole reason of it is to have it there before the hardware is released.

How is that related to my GSoC project of improving support of Intel’s ICH/PCH chipsets? – Not at all. But it is way more fun to hack on something with documentation and my beloved mentor (Carl-Daniel) is way too busy to support me at the moment. 🙄