[GSoC] Better RISC-V support, week #3

Last week, after updating GCC (by applying Iru Cai’s patch) and commenting out uses of outdated instructions and CSRs (most notably eret and the HTIF CSRs), I noticed that coreboot crashed when it tried to access any global variables. This was because the coreboot build system thought coreboot would live near the start of the address space.

I found spike-riscv/memlayout.ld, and adjusted the starting offset. But then I got a linker error:
build/bootblock/arch/riscv/rom_media.o: In function `boot_device_ro': [...]/src/arch/riscv/rom_media.c:26:(.text.boot_device_ro+0x0): relocation truncated to fit: _RISCV_HI20 against `.LANCHOR0'

I played around with the start address and noticed that addresses below 0x78000000 worked, but if I chose an address that was too close to 0x80000000, it broke. This is, in fact, because pointers to global variables were determined with an instruction sequence like lui a0, 0xNNNNN; addi a0, a0, 0xNNN. On 32-bit RISC-V, the LUI instruction loads its argument into the upper 20 bits of a register, and ADDI adds a 12-bit number. On a 64-bit RISC-V system, lui a0, 0x80000 loads 0xffffffff80000000 into a0, because the number is sign extended.

After disassembling some .o files of coreboot and the RISC-V proxy kernel, I finally noticed that I had to use the -mcmodel=medany compiler option, which makes data accesses pc-relative.

Now that coreboot finally ran and could access its data section, I finished debugging the UART block that I promised last week. Coreboot can now print stuff, but it stops running pretty soon.

Plans for this week

This week I will debug why coreboot hangs, and will hopefully get it to boot until the “Payload not found” line again, which worked with an older version of Spike.

Also, Ron Minnich will be giving a talk about coreboot on RISC-V at the coreboot convention in San Francisco, in a few hours.

[GSOC] Panic Room, week #2

How was your last week?

Let’s say that it was a bit unexpected.

I spent the majority of it trying to wrap my head around the ELF (Executable Linkable Format) specification.
I used this new acquired knowledge to improve the utility cbfstool and allow it to extract payloads contained inside a CBFS directly into ELF instead of SELF (commit).

In order to achieve this cbfstool has to do a few things:

Extract the payload from the coreboot image
Parse the segment table contained inside the SELF payload in order to find out how many and which segments are present.
Using the elf_writer API generate a compliant ELF header
Take the content from each segment and copy it to the correspondent ELF section header and configure it accordingly
Once the section table is filled out, use elf_writer to generate the program header table and write out the final ELF

The final results would allow to, for example, easily move payloads from a CBFS to another one without having to re-build the payload, coreboot rom or mess with the build system configuration.
Right now the implementation it’s not complete yet but it works quite well with a good chunk of the payloads commonly used with coreboot such as SeaBIOS, coreinfo, nvramcui and others.
The major hurdles right now are to get the GRUB payload to work and add a way to handle the extraction of a compressed payload.

Wait a minute! Weren’t you working on SerialICE?

You are quite the inquisitive type, aren’t you?

Yes, my main goal is still to continue integrating SerialICE and coreboot.
Unfortunately there have been a few showstoppers this week, first my only test clip broke and now my target, Lenovo x60, stopped working and I am no longer able to flash its BIOS chip.
I already ordered a replacement but it’ll probably take a bit more than a week to arrive.

In the meantime my mentor (adurbin) kindly pointed out the task above to keep me busy while waiting.

What are your plans for the next week?

I plan to finish implementing the functionality described above and test all the remaining payloads.
Hopefully I will also be able to start looking at some of the other tasks that have been suggested to me by my mentors.

That’s it for today, see you next week!

[GSoC] Better RISC-V support, week #2

Last week, I updated my copy of spike (to commit 2fe8a17a), and familiarized myself with the differences between the old and the new version:

The Host-Target Interface (HTIF) isn’t accessed through the mtohost and mfromhost CSRs anymore. Instead, you have to define two ELF symbols (tohost and fromhost). Usually this is done by declaring two global variables with these names, but since the coreboot build system doesn’t natively produce an ELF file, it would get a little tricky.
Spike doesn’t implement a classic UART.
The memory layout is different. The default entry point is now at 0x1000, where spike puts a small ROM, which jumps to the start of the emulated RAM, at 0x80000000. One way to run coreboot is to load it at 0x80000000, but then it can’t catch exceptions: The exception vector is at 0x1010.
Within spike’s boot ROM, there’s also a text-based “platform tree”, which describes the installed peripherals.

“Why does coreboot need a serial console?”, you may ask. Coreboot uses it to log everything it does (at a configurable level of detail), and that’s quite useful for debugging and development.

Instead of working around the problems with HTIF, I decided to implement a minimal, 8250-compatible UART. I’m not done yet, but the goal is to use coreboot’s existing 8250 driver.

Plans for this week

This week, I will rewrite the bootblock and CBFS code to work with RISC-V’s new memory layout, and make sure that the spike UART works with coreboot’s 8250 UART driver. Booting Linux probably still takes some time.

[GSOC] Panic Room, week #1

Who are you?

Hello everyone, I’m Antonello Dettori (avengerf12 on IRC) and I’m the student currently working on improving SerialICE.

What are you working on?

I’m glad you asked.

As I said just a bunch of lines before I’m working on SerialICE, which is one of the main tools used in reverse engineering an OEM BIOS and therefore in understanding the initialisation process that coreboot will have to perform in order to properly run on a target.

The original idea of my proposal was to work towards:

Incorporating the functionality of SerialICE into coreboot.
Allowing for a way to flash a coreboot-running target without a working OS environment.

The situation has changed a bit in the few months after the proposal was written and part of the goals have already been worked on by some of the wonderful contributors in the coreboot community.
I still have plenty of work to do and my mentors already pointed out some of the areas of the project with which I could spend my time.

How was your first week?

Oh boy, you had to go there, didn’t you?

I’ve been kind of a late bloomer regarding this project since only from this week I came to truly appreciate all of the work that goes into making coreboot and SerialICE tick.
I’m therefore still knee-deep in the learning process, but don’t worry, progress is being made on this front.
Unfortunately, this also means that I don’t have any actual code to reach my goals yet.

What will you do during the next week?

I will, hopefully, manage to wrap up my learning “session” with SerialICE and get to finally write some actual (possibly useful) code.
In particular I hope to fix the problem regarding the conflicts in managing the cache and its related registers that occur when coreboot initialises the target but SerialICE is used as the romstage.

That’s pretty much it for now, see you next week!

[GSoC] Better RISC-V support, week #1

Hi, I’m Jonathan Neuschäfer (jn__ on IRC) and my GSoC project for this year is to improve coreboot’s support for RISC-V platforms. RISC-V is a new instruction set architecture (ISA) that can be implemented without paying license fees and is relatively simple.

Coreboot has already been ported to RISC-V in 2014, and has since received a bunch of patches, but since the RISC-V Privileged ISA Specification (which defines things like interrupt handling and virtual memory) is still in flux, it has become unbootable again.

My first first goal last week was to run coreboot in SPIKE, the official RISC-V emulator, and get some console output. I checked out commit 419f1b5f3 (current master) of the riscv-tools repository and built SPIKE from there.

After I patched a few outdated instructions and worked around the fact that the RISC-V binutils port currently included in coreboot targets a newer version of the RISC-V Privileged Spec by hardcoding some Control and Status Register numbers, I finally got coreboot booting until the point where it would jump into a payload, had I specified one.

All patches can be found under the riscv topic on gerrit.

Plans for this week

This week I will update my SPIKE to a version that supports the upcoming Privileged Spec 1.9, which will be released in the next couple weeks. This has the advantage that I don’t need to patch instructions because GCC encodes them differently than SPIKE decodes them. Additionally, I’ll try to get Linux to boot in SPIKE, under coreboot.

Announcing coreboot 4.4

We are happy to announce the release of coreboot 4.4. This is our fourth quarterly release. Since the last release, we’ve had 850 commits by 90 authors adding 59000 lines to the codebase.

The release tarballs are available at https://www.coreboot.org/releases/
There is a 4.4 tag and branch in the git repository.

Log of commit 3141eac900 to commit 588ccaa9a7

Major areas that received significant changes in for this release:

Build system (30 commits) – Add postcar stage, ‘timeless’ builds, extend site-local, test toolchain by version string, update dependencies, catch ACPI errors, l add additional macros.
Toolchain updates (40+ patches) – Update IASL to v20160318 , LLVM to v3.7.1, add GNU make, add nds32le GCC compiler
Lint tools (30 patches) – Update existing lint utilities, add lint tests for executable bit, make sure site-local isn’t committed, add test to break all lint tests.
Payloads (60 commits) – Fixes for libpayload, coreinfo and nvramcui, add new payloads, see below.
Maintainers file – (8 patches) – continue adding maintainers for various areas.
Documentation for adding Intel FSP-based platforms (20 commits)

Mainboards

Added 9 mainboards

asus/kcma-d8
emulation/qemu-power8
google/auron_paine
google/gru
intel/amenia
intel/apollolake_rvp
intel/camelbackmountain_fsp
intel/galileo
lenovo/t420

Existing boards with significant updates

asus/kgpe-d16
google/oak
google/chell
intel/kunimitsu

Changes in chips

Added 1 new architecture

power8

Added 1 processor

qemu-power8

Added 5 socs

intel/apollolake
intel/fsp_broadwell_de
intel/quark
marvell/armada38x
rockchip/rk3399

Existing chip areas with many changes

cpuamd/mct_ddr3
drivers/intel/fsp2_0
northbridge/intel/sandybridge/raminit
soc/intel/apollolake
soc/intel/fsp_baytrail
soc/intel/skylake
soc/mediatek/mt8173

Added 1 new vendorcode directory

siemens

Submodules

Added 1 submodule

chromeec

Updated 3 submodules

3rdparty/arm-trusted-firmware (329 commits)
3rdparty/vboot (28 commits)
util/nvidia/cbootimage (13 commits)

Other

Added 4 payloads

depthcharge: For ChromeOS verified boot
iPXE: For network booting
Memtest86+: Updated with fixes for correctly testing coreboot with payloads
U-Boot (Experimental): Alternate payload for booting an OS

Added 6 utilities

archive – Concatenates files into a single blob with an indexed header
chromeos – Download and extract blobs from a ChromeOS image
futility – vboot Firmware utility
intelmetool – Shows information about the Intel ME on a platform.
marvell/doimage_mv – No usage notes
post – Simple utility to test post cards

coreboot statistics

Total Commits: 850
Total authors: 90
New authors: 28
Total Reviewers: 40
Total Submitters: 17
Total lines added: 74054
Total lines removed: -15056
Total difference: 58998

coreboot changelog March 2 – March 15

This changelog covers 187 commits in the two week period between March 2, 2016 and March 15, 2016. (c77e0419 – 80547369)

Once again this time, we had many changes in the payloads area. We added a memtest86+ git repository, and set it up as a secondary payload within the coreboot build process. SeaBIOS updated the stable version from 1.9.0 to 1.9.1 and has a new option to build from any specified commit instead of just master or stable branches. Google’s depthcharge payload was added for ChromeOS builds, and the coreinfo payload started getting some updates – removing obsolete pieces, fixing the makefile, and correcting issues with cbfs.

The MediaTek MT8173 ARM based SOC and the Google OAK board using it received a significant number of patches, adding trusted firmware support, and initialization routines for memory, USB, audio, TPM, GPIOs, I2c and RTC.

Several other groups of patches were to perform cleanup for various chipsets. One series unified and fixed up the UDELAY settings, many of which were incorrectly specifying TSC delays which weren’t supported by those platforms. Other sets removed code #includes of C files, merged the MRC cache implementations into a single common version, and combined Sandybridge & Ivybridge LVDS implementations. The FSP version of Intel’s Bay Trail was updated to mirror the non-FSP implementation, enabling LPE and LPSS in ACPI mode. The plan with Bay Trail is to make the two versions as similar as possible, then work to combine the directories and use common code for both.

Intel has started adding support for their Xeon D (Broadwell DE) processor. So far only the vendorcode has been merged. The coreboot code is another 4700 lines of chipset code and 800 lines of mainboard code, so that’s taking some time to get reviewed.

The patches bringing up the Quark and Apollo Lake Intel chips continued, with Quark getting minor updates and Apollo Lake continuing to add core functionality like memory init and the various calls into the FSP.

Additional work was done on Skylake as well, updating the FSP parameter table, adding a Voltage Regulator mailbox command, and adding clock gating for the 8254 timer.

Utilities only got a few changes this time. The cbmem utility got a fix a regression and correctly scale the timestamp values and an option to change the SPI ROM chip sizes was added to ifdtool. Cbfstool got a couple of fixes as well, making sure the structure sizes are the same whether compiled for 32-bit or 64 bit platforms, and zeroing out unused Linux parameters.

AMD’s native memory initialization got some more cleanup and several fixes, restoring DQS delay values on a failed loop, and making sure that both read and write training pass before proceeding to the next training phase instead of continuing when either one passed.

SMBIOS changes included a patch to add SMBIOS type 17 (Memory) fields to the Sandy Bridge / Ivy Bridge platforms, and another patch to fix the length calculated for those fields for every platform. A third patch added the names of several different DIMM vendors.

The X86 bootblock renamed several symbols for clarification, removed some unused code, and marked the reset vector as executable so it would show up in objdump.

We had a slew of patches from new authors merged in the past two weeks. Welcome to all new authors and thank you to everyone.

Antonello Dettori had 3 patches merged, allowing SeaBIOS to be build from any revision, and cleaning up early serial on the roda rk9 and amd thatcher platforms.
Bayi Cheng wrote a patch adding NOR flash DMA read routines for the Mediatek MT8173.
Georg Wicherski updated and added Google’s auron paine board.
Huki Huang modified the ChromeOS wifi regulatory domain to use the region key from VPD.
Jan Tatje updated the Intel Firmware Descriptor tool (iftdool) to allow the SPI rom sizes to be updated.
Jitao Shi added the parade ps8640 MIPI-to-eDP video format converter driver.
Jonathan Neuschäfer had an astounding 7 patches merged in his first couple of weeks submitting to coreboot. He fixed a syntax error in buildgcc, and updating several areas in coreinfo.
Jun Gao did I2C work on Mediatek MT8173 and on Google’s Oak board,
Lance Zhao had a pair of patches for Intel’s Apollo Lake reference board, setting up the devicetree, and adding memory training configuration.
Medha Garima added runtime SD card detection to Intel’s Kunimitsu board.
Milton Chiang had a patch updating the infracfg register map for the Mediatek MT8173.
Peter Kao wrote a pair of patches adding DRAM initialization to the Mediatek MT8173 and Google’s Oak board.
PH Hsu set up 4GB mode on Mediatek MT8173 and Google’s Oak board.

coreboot statistics

- Total commits: 187
- Total authors: 44
- New authors: 13
- Total lines added: 15724
- Total lines removed: -1750
- Total difference: 13974

Added 1 mainboards: google/auron_paine
Added 1 new driver: parade/ps864C

=== Top Authors - Number of commits ===
Martin Roth                  27 (14.439%)
Stefan Reinauer              24 (12.834%)
Andrey Petrov                18 (9.626%)
Aaron Durbin                 15 (8.021%)
Yidi Lin                      8 (4.278%)
Timothy Pearson               8 (4.278%)
Jonathan Neuschäfer           7 (3.743%)
Patrick Rudolph               7 (3.743%)
Leroy P Leahy                 6 (3.209%)
Alexander Couzens             5 (2.674%)
Duncan Laurie                 5 (2.674%)
Total Authors: 44

=== Top Authors - Lines added ===
Peter Kao                  3750 (23.849%)
Andrey Petrov              2536 (16.128%)
York Yang                  2509 (15.956%)
Georg Wicherski            2214 (14.080%)
Alexandru Gagniuc           409 (2.601%)
Ben Gardner                 406 (2.582%)
Leroy P Leahy               384 (2.442%)
Daisuke Nojiri              373 (2.372%)
Bayi Cheng                  314 (1.997%)
Martin Roth                 256 (1.628%)

=== Top Authors - Lines removed ===
Alexander Couzens           309 (17.657%)
Leroy P Leahy               255 (14.571%)
Stefan Reinauer             207 (11.829%)
Aaron Durbin                162 (9.257%)
Jonathan Neuschäfer         156 (8.914%)
Timothy Pearson             127 (7.257%)
Julius Werner                93 (5.314%)
Zheng Bao                    87 (4.971%)
Martin Roth                  66 (3.771%)
Andrey Petrov                58 (3.314%)

=== Top Reviewers - Number of patches reviewed ===
Martin Roth                  82 (43.850%)
Stefan Reinauer              62 (33.155%)
Paul Menzel                  45 (24.064%)
Aaron Durbin                 28 (14.973%)
Andrey Petrov                13 (6.952%)
Patrick Georgi               12 (6.417%)
Furquan Shaikh                6 (3.209%)
Timothy Pearson               4 (2.139%)
Ronald G. Minnich             4 (2.139%)
Alexander Couzens             4 (2.139%)
Total Reviewers: 22

=== Submitters - Number of patches submitted ===
Martin Roth                  85 (45.455%)
Patrick Georgi               47 (25.134%)
Aaron Durbin                 24 (12.834%)
Stefan Reinauer              20 (10.695%)
Vladimir Serbinenko           4 (2.139%)
Werner Zeh                    2 (1.070%)
Timothy Pearson               2 (1.070%)
Zheng Bao                     1 (0.535%)
Leroy P Leahy                 1 (0.535%)
Ronald G. Minnich             1 (0.535%)
Total Submitters: 10

GSoC 2016

The coreboot project is proud to announce that it has been selected as one of the 2016 Google Summer of Code (GSoC) mentor organizations. GSoC is a program designed to encourage university students age 18 and older to participate in open source projects. This is done by paying students to partner with experienced mentors from the selected open source projects to work on a specific project chosen by the student. This helps the mentor organization by encouraging participation and getting tasks done while helping the student get involved in open source, add projects to their resume, and learn from experienced open-source participants.

Student applications begin next Monday, March 14th, 2016, and close on Friday, March 25th. Accepted student projects will be announced on April 22nd. Any students who are interested in applying for a coreboot, flashrom, or SerialICE GSoC project should look at the GSoC student terms page, and at both coreboot’s GSoC page and the coreboot / Flashrom / SerialICE projects page. Projects are not limited to what is currently listed here. Students typically select from these, but if you have other ideas of projects in our space, we’d love to hear about them.

As noted above, coreboot acts as an umbrella organization for other firmware related open-source projects, currently supporting Flashrom and SerialICE. If there are other firmware related projects who would like to be included under the coreboot project for GSoC, please contact the project administrators, Patrick Georgi or Martin Roth.

Finally, if you are a developer who would like to volunteer as a mentor, please contact us. First year volunteers will generally be teamed up with experienced mentors, so don’t worry about not having previous experience. If you’re interested, you can read more about mentoring expectations in the GSoC mentoring Guide.

coreboot changelog Feb 17 – March 1

This changelog covers 105 commits in the two week period between February 17, 2016 and March 1, 2016. (6a622311 – 163506a8)

We’ve entered a lower volume period for patches being submitted, so for a while, blog posts will be every two weeks instead of every week. Once we get above 100 patches a week, blog posts will be weekly again.

Payloads got some attention during this period, adding a way to include additional modules into the GRUB2 build. An option was added to build and include coreinfo as a ‘secondary’ payload, allowing it to be run from another payload. We also added U-Boot as a coreboot payload. This is currently still just in development, and needs additional work before it will act as a generic payload for all platforms.

We added LZ4 compression to the build with runtime decompression for cbfs. LZ4’s speed should be roughly the same as LZMA, trading a smaller compressed size for slightly slower decompressoin. LZ4’s main advantage is that it requires much less memory to do the decompression, allowing for compression of stages that couldn’t previously be compressed.

The suite of board-status scripts got several updates, fixing timestamp handling for the sanitized path names, handling when the script is run as super-user in a better way, and adding a script that will set up a Ubuntu Live-image to allow users to more easily run the board-status script.

In the build tools and utilities, we had some fixes for the toolchain builder, updating the GDB builds for x86_64 and MIPS. A couple of scripts were also added. One utility downloads and extracts binary blobs from Chrome OS recovery images, and the other new script allow easier testing of POST cards.

Intel based boards and chipsets received a large percentage of the patches for the past two weeks:

The Galileo board and Quark chip had several pieces new added, along with additional documentation for those changes. Major pieces done were to set up the basic registers, in the ACPI FADT, setting up the memory map, and enabling the UART.

We received the final set of patches to finish out the changes combining many of the the Intel GPIO initialization routines into a single common set of functions. The autoport script was updated to use the common GPIO functions.

Sandy Bridge / Ivy Bridge memory initialization also continued to receive updates, adding support for XMP profiles in the SPD, updating logging, and fixing some bugs.

Intel’s Skylake chipset and boards were updated to enable Hardware P-state control (HWP) based on Intel’s Speed Shift Technology (SST). Another change to Skylake platforms increased stolen memory for graphics to 64MB.

Intel Bay Trail got a couple of updates, adding a fix for issues with displayport on the FSP version, and adding IOSF access support to the reg_script module.

Intel Apollo Lake had several more foundational pieces added to the codebase. Many more patches for Apollo Lake are expected in the next couple of weeks.

On the non-X86 side, the instructions for running the Arm7 Qemu board were updated, and the memory map was corrected.

RISC-V got a couple of patches, adding additional debugging, and fixing some inline asm code.
The coreboot project would like to recognize another pair of developers who have hit major milestones in the past two weeks:

Lee Leahy just reached his 100th commit merged into coreboot.org. Lee is a developer with Intel who has been working on coreboot for about a year and a half. He has worked on many of the recent intel chipsets, and is currently adding support and documentation for the Intel Galileo board and Quark chips in a way that each step of the process can be tested and verified. While this takes significantly more effort than the typical method of porting, it should result in a better platform.

Tobias Diedrich has just had his 50th patch merged. Tobias has been contributing patches to coreboot for over five years, and his patches have spanned a number of boards and chipsets.

Finally, please welcome our newest authors:
– Andrew Waterman contributed the pair of RISC-V patches.
– Joe Pillow added the Chrome OS recovery image script.

coreboot statistics

- Total commits: 105
- Total authors: 25
- Total lines added: 13396
- Total lines removed: -3127
- Total difference: 10269

Added 1 mainboard: emulation/qemu-power8
Added 1 processor: qemu-power8

Submodule updates:
- 3rdparty/arm-trusted-firmware (329 commits)
- 3rdparty/vboot (2 commits)

=== Top Authors - Number of commits ===
Leroy P Leahy                20 (19.048%)
Aaron Durbin                 11 (10.476%)
Patrick Rudolph               8 (7.619%)
Patrick Georgi                8 (7.619%)
Martin Roth                   8 (7.619%)
Stefan Reinauer               5 (4.762%)
Vladimir Serbinenko           5 (4.762%)
Denis 'GNUtoo' Carikli        4 (3.810%)
Julius Werner                 4 (3.810%)
Werner Zeh                    4 (3.810%)
Duncan Laurie                 4 (3.810%)
Ronald G. Minnich             4 (3.810%)
Total Authors: 25

=== Top Authors - Lines added ===
Julius Werner              7602 (56.748%)
Leroy P Leahy              1255 (9.368%)
Ronald G. Minnich          1097 (8.189%)
Stefan Reinauer             990 (7.390%)
Werner Zeh                  479 (3.576%)
Patrick Rudolph             406 (3.031%)
Damien Zammit               336 (2.508%)
Martin Roth                 293 (2.187%)
Aaron Durbin                232 (1.732%)
Joseph Pillow               218 (1.627%)

=== Top Authors - Lines removed ===
Stefan Reinauer            1662 (53.150%)
Patrick Rudolph             936 (29.933%)
Julius Werner               154 (4.925%)
Aaron Durbin                128 (4.093%)
Leroy P Leahy                93 (2.974%)
Damien Zammit                21 (0.672%)
Patrick Georgi               20 (0.640%)
Vladimir Serbinenko          17 (0.544%)
Tobias Diedrich              15 (0.480%)
David Hendricks              13 (0.416%)

=== Top Reviewers - Number of patches reviewed ===
Martin Roth                  43 (40.952%)
Stefan Reinauer              33 (31.429%)
Paul Menzel                  30 (28.571%)
Aaron Durbin                 13 (12.381%)
Andrey Petrov                 8 (7.619%)
Furquan Shaikh                8 (7.619%)
Patrick Georgi                6 (5.714%)
Ronald G. Minnich             5 (4.762%)
Timothy Pearson               4 (3.810%)
Patrick Rudolph               3 (2.857%)
Total Reviewers: 18

=== Top Submitters - Number of patches submitted ===
Martin Roth                  40 (38.095%)
Leroy P Leahy                18 (17.143%)
Stefan Reinauer              13 (12.381%)
Patrick Georgi                8 (7.619%)
Aaron Durbin                  8 (7.619%)
Vladimir Serbinenko           5 (4.762%)
Ronald G. Minnich             4 (3.810%)
Julius Werner                 4 (3.810%)
Werner Zeh                    3 (2.857%)
Total Submitters: 11

coreboot changelog Feb 10 – Feb 16

This changelog covers 77 commits in the week between February 10, 2016 and February 16, 2016. (318ef96a – 0188b139)

Many of the big changes this week surrounded native initialization of the Sandy Bridge/Ivy Bridge platforms. We got patches to change platforms which had been previously based on Intel’s MRC blob to build with either the MRC or coreboot’s native memory initialization. We also got patches combining the Intel GPIO initialization for various chipsets into a single common set of functions.

Continuing the series from the past several weeks, we merged patches for the Intel Apollo Lake, Skylake, and Quark platforms. Apollo Lake got a skeleton for its initial mainboard, and added code to support GPIO init. Quark added FSP initialization and MTRR support. The more mature Skylake SoC received some minor fixes for graphics and to finalize SMM inside coreboot.

Another of the Intel FSP platforms, the FSP version of the Intel Bay Trail codebase was updated to support version 5 of the Bay Trail FSP, which should be released to the Intel website shortly.

On the ARM side, we got several small fixes, and a patch to verify consistency of the page table descriptors. This sounds like it will help prevent ‘interesting’ debug sessions due to conflicting memory types for the same memory area.

The build system and toolchain received fixes for issues downloading git submodules, for the gitconfig make target, and for building under paths that have an ‘@’ character in their name. A couple of changes were added to make Kconfig’s strict mode slightly less strict and more user friendly.

Two new lint tools were added this week, one to make sure that the site-local directory doesn’t get pushed and committed, and another that checks over the Kconfig files for various issues.

Other changes this week included a change to allow bootblock code to use CAR_GLOBAL variables, and continued work updating and adding license headers throughout the coreboot codebase.

Finally, I’d like to recognize two contributors this week:

Damien Zammit (damo22) reached his 50th commit merged into coreboot last week. His contributions have included the addition of two complete platforms, the Intel D510MO board with the Intel Pineview Atom processor, and the Gigabyte GA-G41M-ES2L board with the Intel x4x northbridge and Intel i82801gx southbridge. Damien joined coreboot in July of 2013, but has recently become very active.

Vladimir Serbinenko (phcoder) just broke 550 patches merged with his work moving Sandy Bridge/Ivy Bridge MRC platforms to native init mentioned earlier. Vladimir joined coreboot just under 3 years ago, and has been a fantastic contributor to the community.

Thanks to both of you, and to all the rest of the coreboot contributors.

coreboot statistics

- Total commits: 77
- Total authors: 16
- Total lines added: 6494
- Total lines removed: -1569
- Total difference: 4925

Added 1 mainboard: intel/apollolake_rvp

=== Top Authors - Number of commits ===
Patrick Georgi               12 (15.584%)
Vladimir Serbinenko          12 (15.584%)
Aaron Durbin                  9 (11.688%)
Julius Werner                 7 (9.091%)
Andrey Petrov                 6 (7.792%)
Duncan Laurie                 5 (6.494%)
Martin Roth                   5 (6.494%)
Leroy P Leahy                 4 (5.195%)
Alexandru Gagniuc             3 (3.896%)
Patrick Rudolph               3 (3.896%)
Yves Roth                     3 (3.896%)
Stefan Reinauer               3 (3.896%)

=== Top Authors - Lines added ===
Ruilin Hao                 2528 (38.928%)
Andrey Petrov               817 (12.581%)
Vladimir Serbinenko         681 (10.487%)
Yves Roth                   678 (10.440%)
Leroy P Leahy               451 (6.945%)
Patrick Rudolph             355 (5.467%)
Alexandru Gagniuc           242 (3.727%)
Aaron Durbin                213 (3.280%)
Patrick Georgi              194 (2.987%)
Julius Werner               131 (2.017%)

=== Top Authors - Lines removed ===
Vladimir Serbinenko         892 (56.851%)
Aaron Durbin                247 (15.743%)
Julius Werner               244 (15.551%)
Patrick Georgi               68 (4.334%)
Yves Roth                    64 (4.079%)
Martin Roth                  13 (0.829%)
Duncan Laurie                12 (0.765%)
Patrick Rudolph              11 (0.701%)
Andrey Petrov                 7 (0.446%)
Ruilin Hao                    4 (0.255%)

=== Top Reviewers - Number of patches reviewed ===
Martin Roth                  31 (40.260%)
Aaron Durbin                 16 (20.779%)
Patrick Georgi               13 (16.883%)
Paul Menzel                  13 (16.883%)
Alexandru Gagniuc            12 (15.584%)
Stefan Reinauer              11 (14.286%)
FEI WANG                      3 (3.896%)
York Yang                     2 (2.597%)
Andrey Petrov                 2 (2.597%)
Total Reviewers: 15

=== Submitters - Number of patches submitted ===
Martin Roth                  25 (32.468%)
Aaron Durbin                 19 (24.675%)
Patrick Georgi               15 (19.481%)
Vladimir Serbinenko           6 (7.792%)
Stefan Reinauer               6 (7.792%)
Julius Werner                 5 (6.494%)
Ronald G. Minnich             1 (1.299%)
Total Submitters: 7