Well my progress is not so shiny as other students. Looks like I overestimated my capabilities in my project proposal. I ended up with long exam session, lurking by reading coreboot mailing list (like an old cow), reading stuff about computer architecture, making hardware tools and trying to understand how git works
Done some patches, unfortunately, nobody likes it
Temporary libpayload fixes for flashrom as a payload
Flashrom as a payload with usb flash drive support
SerialICE for coreboot
Triggering another payload
For the second half of GSoC:
I’m working on “carFlashrom” (Yep, sounds a bit french) project:
If this project is possible, then flashing would be possible without working RAM.
I would like to receive some response to my mails in the list as I am confused with my project goals, what others do think? I need some alternative goal if this is not feasible.
Give me some thoughts.
Bonus for readers: this one might be used with flashrom as rayer_spi. Modify flashrom source according to pinout and bits of par port registers:
I used m74hc244 from ST, even though parport signals are 5V, the chip is working right with VCC 3.3V.