Ever heard about the bifferboard? It is a small RDC x86 SoC with 150MHz 486 compatible CPU, 8MB flash and 32MB RAM, ethernet and TTL serial line and a few GPIOs. It comes with very tiny loader called biffboot. Quite natural target for coreboot and u-boot. My flatmate purchased one but never had actually time to do anything with that so here it comes. Continue reading Bifferboard porting
I just found out that nobody wrote a few lines about this year’s FOSDEM 2011. This year we had a booth (aka a “table”) in one of the buildings. We had total 4 speeches. I did one lightning talk about the coreboot and x86 init (video) and a lecture about coreboot and its speed. Carl-Daniel Hailfinger had lightning talk (video) and a talk about RAM Cold Boot Attacks The talks had a great success and a lot people attended. Continue reading FOSDEM 2011 photos
U-boot is bootloader on ARMs, PowerPCs and other platforms, it has a nice set of commands and in general it feels like a small operating system. I’m not certainly sure if it is good direction, please feel free to compare with UEFI 😉 but I simply miss it on x86. I work at SYSGO with u-boot in daily basis and even port it to different boards/platforms. The x86 is no easy to init and I think this is the reason why there is only one x86 board in whole u-boot tree. This board is called eNET and it has a AMD ELAN SC520 SOC. But luckily, with coreboot we can init much more x86 boards and this leads to natural conclusion to have the u-boot as the coreboot payload. I would like to share with you part of this “fantastic” hacking journey to make it happen. Continue reading u-boot as coreboot payload
Although this article is about Coreboot I start from beginning. Once upon a time (November 2009) there was nice idea to make SerialICE work through the Ethernet link. Reason is simple, it is slow and Ethernet is way faster. I started to investigate if there is some network adapter which can be used without the need of RAM.
If you check the documentation of most Ethernet chips, the packet descriptors are always located in main memory and they just use DMA to transfer data to/from the FIFO inside the card. I tried some sophisticated google queries to find out if there is some adapter with internal SRAM, and after a while I found one. Continue reading Coreboot console over Ethernet