spice payload: Before MidTerm GSoC report

My very first task on gsoc was to make buildrom work with latest codes from coreboot, with that I changed how it used to build coreboot. First I introduced the coreboot kconfig options to buildrom so the user can configure and choose the options for coreboot in the same mainmenu as buildrom.

 
Some small changes was introduced as a consistent pattern to name the kernel mk files and the possibility to checkout source code with https:// or svn://.
Updated some packages mk files to comply some patterns I introduced.

 
I still have some changes to introduce but I think it`s already usable. I might push the final bits in the next few days whenever I get a chance to work out my patches.

GSoC 2011: flashrom + filo = ?

 

The answer is flashrom payload, which is capable flashing roms out of usb stick. If you use seabios, you will be able to choose to run this payload instead of booting os. It might be worth for payload developers if we would have a small payload for selecting other payloads out of CBFS 🙂

Patches are here. Sorry for weird stuff there 🙂

 

My GSOC project is not going well, I end up with problems almost everywhere 🙁 (Only the good thing is that my exams went well). I spend my time trying to understand what is going on. Yesterday I was running an overflowing code allmost all day, until I found out what is wrong… My E350M1 is still not working (coreboot doesn’t run with 512 kB chip). So I have ordered some chips from ebay. While I’m waiting I have made some PCB adapters to make a dual flash device. Also made additional PCB for RS232<->UART<->USB interface.

I would better go coding… Bye!

AMD contributes A-series Family 12 (Llano), Hudson-2 (SB900), and Torpedo mainboard

Frank Vibrans from AMD pushed commits for the Fam12 and SB900 code into gerrit last week. This is just days after the official A-series release. The review has started. Feel free to help out. The gerrit links are:

http://review.coreboot.org/#change,54

http://review.coreboot.org/#change,53

http://review.coreboot.org/#change,52

http://review.coreboot.org/#change,51

http://review.coreboot.org/#change,41

http://review.coreboot.org/#change,40

 

GSoC2011(Week 5): the layout of coreboot rom and cbfstool for ARM

Hi all. How time flies. It has been 4 weeks since my last post. During this month, I have finished the design and implement of bootblock, Rom structure and cbfstool for ARM. Following I will show my changes to you all.
Continue reading GSoC2011(Week 5): the layout of coreboot rom and cbfstool for ARM

GSoC 2011: (week 2) Coreboot Spice Payload

I still haven’t had a good progress on my project, my first step is to work around the buildrom system.

I got to bring fully the coreboot Kconfig options to buildrom, since I don’t want to manually update it after coreboot updates I decided to write a small program to parse the coreboot Kconfig files. I found some api’s to help but I god stuck with that first task since none of them actually help me so much. A simple task became so complex and took me more time than I wanted(I started to update the api’s and change it acordingly to my needs, but well my project is not a kconfig api).

For a better and simpler solution I sat down and wrote a small shell script to run all the Kconfig’s and merge it into a single Kconfig.coreboot.

Now the next task is to change the building flow, how coreboot is fetched, patched and built.

For the final image and package I still want to get it all on the flash, I’m working on finding a solution to fit it as small as possible.

I found it would be interesting to use Kdrive to make the image smaller since it’s a minimal X server, but it’s unmaintained and we can build a thin X server from upstream.
For code sharing and analisys I setup a git repository so my mentor can comment on what I’m writing.
Now I have to move I bit faster.

GSoC2011(Week 1): Analysis of U-boot ARM boot code

This is such a busy week. At the end of last week, I have just ordered my OpenRD-Ultimate box but sadly it will be delivered at the end of June. So if I just wait for that box, I will not be able to test my code. That’s terrible! After talking with my mentor, I decided first porting coreboot to RealView Versatile/PB926EJ-S board then to OpenRD-Ultimate. Since qemu can emulate PB926EJ-S, I can test my code on it quickly and freely. After this work, the basic layout, libs and headers for ARM are ready to use. So I can start to port coreboot to OpenRD-Ultimate then.
Continue reading GSoC2011(Week 1): Analysis of U-boot ARM boot code

GSoC 2011: Coreboot Spice Payload

This year I was accepted on gsoc – and I`m excited – to work in a project to make corebook a spice client. The idea is to use buildrom to pack everything.

Once buildrom has been unmaintained for quite some time now I`ll need to work around it before working on the spice bits.

 

Spice

Yeah! when I say spice I mean the remote and virtualized desktop protocol, originally developed by Qumranet now acquired by Red Hat.
The basic idea is to make a client run from a minimal environment. We`ll be working on a LAB(Linux as bootloader) solution.

 

Initial steps

As I said above, we need some work around buildrom system, the coreboot buildsystem has migrated to kbuild on the stable code and lots of things have changed with it.
Both buildrom and coreboot work with kbuild with that I`m writing a small python piece of code to parse coreboot`s Kconfig files and then arrange it into buildrom source code. I also need to 1) monitor the coreboot Kconfig files changes so I run the parser again and 2) change the coreboot build calls.
With all the kconfig arranged the buildrom user needs just to set the rom properties including the coreboot options(since those options are passed to coreboot build).

The kernel configs also need some attention it`s statically set for each board, I haven`t come with a better solution for this till now.

 

Hardware and new toys

I have ordered an ALIX.3D3, a flexyICE and a new desktop computer. The first 2 are comming from EU and will be dispatched later on May. The new desktop computer I get till the end of the week(before the gsoc bonding period end).

 

Now, let`s rock.

GSoC2011 Project: Porting coreboot to ARM architecture

I am so excited that my idea on porting coreboot to ARM architecture has been accepted by GSoC project this year. First, let me introduce myself to you all. I am now a junior student at Hebei University of Technology, People’s Republic of China. My major is Computer Science and Technology. Although my courses are almost focus on high-level software development like database system and software engineering, I am a fan of low-level development. I taught myself IA32 and ARM architecture last year. And during this summer, we will porting coreboot to ARM and make it a new bootloader for ARM.

Those days, I am studying the building system of coreboot deeply, and I am trying to add cross-compile toolchain support to it. Developers has created such a great system and I want to make it greater. 🙂

Thanks for reading my project and any comment is welcome.

GSoC project: Coreboot panic room. Diagnostics (also remote flashing)

I’m very excited to announce my GSoC project which is intended to bring some light for coreboot users. To begin with, I would like to introduce myself. I’m 20 years old student living in Lithuania. I’m studying Informatics Engineering at Kaunas University of Technology. This year we have two interesting modules here: one about operating systems and the other is introduction to computer architecture, which is crucial for learning coreboot. Some time ago I have played with avr microcontrollers, so I have good soldering skills. One day during my free time I thought:

What the hell my old computer’s bios is so badly written that it can’t boot from usb flash and it can’t suspend correctly on Linux? I have a laptop that is running bios stuff more time than the old computer. I thought I can’t live with that and then I found coreboot 🙂 I was very excited that it was so configurable, so open alternative 🙂

Not to waste time on cheap talks, here is my project:

To help developing coreboot code, we have to set-up remote diagnostics (also flashing) interface in coreboot. We will be a able to renew bricked board through serial port or even do some research through registers in case of panic(). This will enable easier development of CAR, chipset, payloads code.

Abbreviations used later:
TARGET – machine running coreboot;
HOST – machine running serial port application, connected to TARGET through serial port
The platform that I will use for development is traditional x86. In case coreboot is supported on ARM, I will be hapy to buy one board to make my code working on both platforms.

 

There will be a diagnostics shell, similar to Serial ICE (or LLshell). Invocation of the shell may occur at any time (when we have (cache or ram) memory or not). It would be invoked by (we should discuss this):
1) serial port data received interrupt (HOST triggers diagnostics mode)
2) if user specified it in code (we may add something like checkpoints in coreboot’s code where TARGET will send command through serial port to HOST and if receives the answer – it enters diagnostics mode)
3) in case of panic() invocation (or something like die())

 

In that shell’s loop we will be able:
1) to run the code instructed through serial port (like Serial ICE): manage register contents, do some research or even like Carl-Daniel suggested to initialise CAR
2) to flash memory through serial port, when we have some memory (CAR or RAM) initialised. Some generic flashing code will be pumped through serial port to memory and then executed.

 

Some small specific goals:
1) analyse different code handling schemes in cases of memory we have (no memory, CAR, RAM)
2) define how Serial ICE will be integrated to coreboot
3) integrate defined Serial ICE stuff to coreboot as our new shell
4) add memory handling funcions to our new shell (for checking how much memory we have, and if we have – for uploading code to memory)
5) analyse flashing protocols
6) develop uniform flashing scheme (for SPI, parralel flash…) define what commands are required, where these commands should reside.
7) make serial port application for HOST (maybe we will use flashrom’s serprog code, it might require enhancing)

 

These are just milestones, some points may change after deeper investigation, when we will have something done.
We may experience the risk of problems in different operating modes when having different memory (no memory, CAR, RAM).

 

Yesterday I was looking at flashrom sources. People have done very good job in preparation for porting it to libpayload. Maybe I should concern making a complete flashrom port on libpayload?
Anyway, thanks for reading about my project. You are welcome to post some comments (maybe on the mailinglist). Your experience would be helpful.
Thanks to our mentors for their patience 🙂