filo payload infrastructure

after several times long discussion with marc. We finally decide to make the filo kconfig as below rules:

1) move filo source code to coreboot/payloads. We should put all of there payloads under this directory right?

2) check the filo libpayload configuration before loading kconfig. The design of the payload infrastructure is gonna to make libpayload be included, but the only method for that is use the makefile “source” command, so we should tell this “source ” where this libpayload is. if the filo located in coreboot/payloads/, then for filo the payload must be under the path “../libpayload”.

3) merge the libpayload configuration into filo payload configuration, after loading libpayload kconfig under the filo kconfig, after this configuration all of the configuration are saved in the default .config file. Then copy the whole .config into libpayload directory. these configuration about filo may be useless for libpayload, but it does not matter, which will not influent the libpayload installation.

4) the next step may be check if there is any conflict between the libpayload and the other paylaods.

successfully porting coreboot to Jetway PA78VM5

I would like to say the first public mainboard porting has already successfully  been done. The whole work also including fintek f71863fg superio supporting. I would like to see the linux login shell shows on the screen. The vgabios is still working under the coreboot and payload process. But it always caused blank or flashing some nonsense character. I really did not know why. the VGA is extracted from the AMI bios. the strange things in that original vbios has an different device id  with (1002,9611). it is (1002,9610). As is known, 0x960 is the 780 vbios (HD3200), but Jetway PA78VM5 has an 780v(HD3100)vbios. I changed the vbios’s device id to make coreboot can load it correctly. it worked, but seems did not work very fine.

the other ongoing progress is digging the coreboot fam10 problems. the latest coreboot can not run very well with most of 780 family mainboard which including mahogany. So i should dig into the code to check out the which revision caused it.

In the next week, i will begin my next mainboard porting which is got from L84Supper. Thanks to him for sending me the board. After i know that shinner coreboot code can not be released, i should trying much more public mainboard porting.

coreboot porting to jetway PA78VM5 have been 95% successful.

i am  glad to say that the Jetway PA78VM5 mainboard can run coreboot sucessfully. The configuration of Jetway PA78VM5 can be found at PA78VM5.the coreboot+filo can work fine. The kernel began booting, but the only problem is after kernel shows”jumping to **” the serial port stoped showing anything. And i have already set the kernel parameter with “console=ttyS0,115200”

First of all thank olsen provide me this mainboard.

The mainboard have an SPI flash W25X80A, my SF100+testchip SO08 can detect the flash type, but can not erase the flash correctly. After contacted with dediprog engineer. i remove the flash from the board, it seems fine, the programming is fine, but i can not use it with the mainboard unless i can bear removing the flash chip every time i need to rebuild the coreboot. After that, i replace that flash chip with an sst 080b. it worked pretty fine. 🙂

another problem is while the coreboot booting, it stoped while corebooting trying to extract the cbfs files. i debugged this for a long time, finally thanks to patrick, i take his advice remove the $(CBFS_COMPRESS_FLAG).it worked.

the latest problem is that amd famlily10 may have much problem with the current build version.

i should find out what difference between btdc and coreboot public version caused problems.

my next step may focus on this things merge the code, and find out why the kernel did not show the booting message.

i am so glad that coreboot can finally booting the Jetway PA78VM5

libpayload xcompile

after a long time learning and code checking, several things has been done:

1)kconfig language have already been learned,  i learned all of these things from “http://www.kernel.org/doc/Documentation/kbuild/kconfig-language.txt”

2)much clear with libpayload xcompile code and menuconfig things. i reviewed all of the code under libpayload/util.

question is i do not know what interface should be added into the libpayload menuconfig. and i also have an doubt about the coreboot xcompile. why not just put the files into the trunk but instead of making the downloaded with and script?

flashrom 0.9.2 released — Open-Source, crossplatform BIOS / EEPROM / flash chip programmer

The long-pending 0.9.2 version of the open-source, cross-platform, commandline flashrom utility has been released.

From the announce:

New major user-visible features:
* Dozens of newly supported mainboards, chipsets and flash chips.
* Support for Dr. Kaiser PC-Waechter PCI devices (FPGA variant).
* Support for flashing SPI chips with the Bus Pirate.
* Support for the Dediprog SF100 external programmer.
* Selective blockwise erase for all flash chips.
* Automatic chip unlocking.
* Support for each programmer can be selected at compile time.
* Generic detection for unknown flash chips.
* Common mainboard features are now detected automatically.
* Mainboard matching via DMI strings.
* Laptop detection which triggers safety measures.
* Test flags for all part of flashrom operation.
* Windows support for USB-based and serial-based programmers.
* NetBSD support.
* DOS support.
* Slightly changed command line invocation. Please see the man page for details.

Experimental new features:
* Support for some NVIDIA graphics cards.
* Chip test pattern generation.
* Bit-banging SPI infrastructure.
* Nvidia MCP6*/MCP7* chipset detection.
* Support for Highpoint ATA/RAID controllers.

Infrastructural improvements and fixes:
* Lots of cleanups.
* Various bugfixes and workarounds for broken third-party software.
* Better error messages.
* Reliability fixes.
* Adjustable severity level for messages.
* Programmer-specific chip size limitation warnings.
* Multiple builtin frontends for flashrom are now possible.
* Increased strictness in board matching.
* Extensive selfchecks on startup to protect against miscompilation.
* Better timing precision for touchy flash chips.
* Do not rely on Linux kernel bugs for mapping memory.
* Improved documentation.
* Split frontend and backend functionality.
* Print runtime and build environment information.

The list of supported OSes and architectures is slowly getting longer, e.g. these have been tested: Linux, FreeBSD, NetBSD, DragonFly BSD, Nexenta, Solaris and Mac OS X. There's partial support for DOS (no USB/serial flashers) and Windows (no PCI flashers). Initial (partial) PowerPC and MIPS support has been merged, ARM support and other upcoming.

Also, the list of external (non-mainboard) programmers increases, e.g. there is support for NICs (3COM, Realtek, SMC, others upcoming), SATA/IDE cards from Silicon Image and Highpoint, some NVIDIA cards, and various USB- or parallelport- or serialport- programmers such as the Busirate, Dediprog SF100, FT2232-based SPI programmers and more.

More details at flashrom.org and in the list of supported chips, chipsets, baords, and programmers.

I uploaded an svn version slightly more recent than 0.9.2 to Debian unstable, which should reach Debian testing (and Ubuntu I guess) soonish.

Jetway PA78VM5-H porting progress

firstly, thanks to Scott Olsen for supporting the mainboard. PA78VM5 is 780/700/ddr2.

The superio which it used is fintek f71863fg. I have already make all of the code done. but at last i found that i do not have the serial port convert which make me can connect to it.

The following week may be used to 1)extract the vbios. 2)make the linux booting…

i am pretty looking forward that.

Coreboot console over Ethernet

Although this article is about Coreboot I start from beginning. Once upon a time (November 2009) there was nice idea to make SerialICE work through the Ethernet link. Reason is simple, it is slow and Ethernet is way faster. I started to investigate if there is some network adapter which can be used without the need of RAM.

If you check the documentation of most Ethernet chips, the packet descriptors are always located in main memory and they  just use DMA to transfer data to/from the FIFO inside the card. I tried some sophisticated google queries to find out if there is some adapter with internal SRAM, and after a while I found one. Continue reading Coreboot console over Ethernet

Getting TianoCore to work well as a coreboot payload

Hi!  My name’s Robert Austin, and my GSoC 2010 project is to get TianoCore working well as a coreboot payload.   TianoCore is the open source component of Intel’s implementation of UEFI.  TianoCore on it’s own is not a BIOS replacement, but it can do some interesting things, and since a quite a few large companies are already committed to EFI, it makes sense to have an EFI payload as an option in coreboot.

I am very excited about working on this project, and working with the coreboot community.  I will make regular announcements about my progress here on this blog, and I will keep my working code available in a git repository here.  There isn’t anything there yet, but there will be soon.  To anyone who happens to checkout my code during the summer, I welcome any comments or suggestions relating to the style or quality of my code.  I want to write high-quality code, so feedback is appreciated.

AMD 780 mass porting

It is my second year to join GSOC. In this year, i will take in charge of AMD RS780+SB700 mass porting. I would like to write down each progress here between this summer.

Today, the dediprog ISP-Testclip-SO8 has arrived. although it’s pretty expensive, but it seems pretty cute. I have already tested in in BTDC lab, hope it can helps me much more.

Welcome!

Welcome to the coreboot developers’ blog. This will become the place where our awesome Google Summer of Code students will log their progress during this summer. I’m really looking forward to all the great projects we are going to have this year. Of course, if you are a coreboot developer, and want to post here, drop me a note.