GSoC 2011: flashrom part 4 – recap

Final evaluation deadline for this year’s GSoC is in 2 weeks. Most of what i have written in my midterm evaluation is still valid.

We have formulated and sent an email to various Intel representatives in the hope to get at least a few hints regarding ME unlocking (and descriptor semantics). I had the idea to send them a mail earlier, but thought it is an ludicrous attempt from all i have gathered regarding Intel’s cooperation with coreboot. Carl-Daniel suggested giving it a go anyway and it provided me a good excuse to not work on REing until we get an answer. Of course we have not received any reply to date 🙁

So i think it is quite clear that my main GSoC project will fail to be delivered on time. But i won’t vanish after GSoC and i still plan to implement ME unlocking eventually.

What’s up besides the GSoC project?

The integration of my patches still lacks reviewing power. Everyone but Carl-Daniel seems to be not much interested in my work and he has not the time to look at everything i produce. Right now flashrom has about 150 patches requiring some action to merge them. Thereof are 41 from me (TBH there is a number of patches that are just rebased and improved a little bit) and 37 from Carl-Daniel. meh.

With the help of Florian ‘florz’ Zumbiehl i was also able to find, fix and report a bug in dmidecode which has direct influence on flashrom. Due to an error in decoding the chassis type in dmidecode, flashrom falsely declares some boards to be mobile devices, which makes it shout a big warning at the user unnecessarily.

I’ve been also working on rebasing, improving and reviewing (very) old patches of others whose discussions just stopped (for example when contributors did not send improvements). My hope is that this will help us shorting the long patch queue, but i doubt that it will suffice 😉

To conclude (or begin) my recap of my GSoC involvement this year, i’d like to first thank google for doing this. This sounds quite pathetic, especially if one knows me better. But it really got me involved in FOSS development with the intensity i wished for (by providing a monetary motivation to get really started). There was some involvement in the past (bug reports and fixes etc.), but flashrom was apparently a nice target to get more involved and learn a lot, not so much about REing and technical details (as i expected and hoped in the beginning), but regarding project management in FOSS (my own proposal, but also flashrom and its patch queue/processing and “upper management’s” free time constraints), interacting with contributers and users, and mastering git (the latter is quite ironical because flashrom does not use it (yet)). It’s a bit sad, that flashrom does not have more contributers (especially reviewers). This is obviously a problem and it might be the time to discuss the development process as a whole. The question is with whom should i discuss this if no one is there 🙂

Although my formal project will not be finished on time, i think i have served the flashrom project well and from the feedback i received so far, Carl-Daniel is also happy with my work. So i think i can declare it as successful after all and i would like to thank everyone involved (so far).

GSoC 2011: little trip

This might be not a good idea, but I had got bored with my project not going well, so I eventually got on trip, through “FOSS and friends” 🙂 I have had some headache with nouveau driver, till I understood that deprecated version was installed. Tried to install a package, which got me in a geometric progression of required dependency packages 🙂 I have filed a bug for LibreOffice, and got one future TODO for “reverse enginering” how exactly CUPS works with one of the label printers we have here as it needs a slight modification. The best thing I have done is started reading a book and building “Linux From Scratch (LFS)”. It’s great while building a package you are accompanied with a short page of info about it, not all manual 🙂 Also I have found out that I don’t have good stuff to read, except that 1k pages book about Linux internals 🙂 While looking at the freenode chatrooms list I have found this resource about c language: http://www.iso-9899.info – all it needs is time for reading everything 🙂

 

My project progress is really slow. As Marc suggested I have done some work to reduce stack usage: wrapped functions to read and use file by 256B peaces (somewhat default granularity). But that still needs testing and cleaning up. Also I need to cleanup my previous work that I haven’t submitted to the list, which enabled running code in car (even though not completely working, as mtrr settings might be wrong or more problems still there).

AMD adds Family10 G34 coreboot support

AMD has added the Family10 G34 support to coreboot. This new support located in the AGESA vendorcode area. This AGESA code should be used for new Family 10 development. The initial development platform is the Super Micro H8QGI+-F mainboard.

 

Thanks to Kerry and Frank @ AMD for the submission.

 

A small side note, this addition put coreboot tree at over a million lines of code.

 

GSoC2011: coreboot spice payload, OE and rootfs

As stated in my midterm report I’m working this first 2 weeks after midterm to work on building the payload image. I wanted to hardcode everything but we(my mentor and I) understood it would be better to use something like OpenEmbedded for that.

 
This first week I studied OpenEmbedded. I tested many distributions starting with angstrom, they showed too heavy for our purpose. After those tests I found micro and realized it would be a better start.

 
With that I’m working around micro to build our own distro, I’m adding X11 dependencies and right now I’m packing the spice client and its dependencies. In the end of the week I must have sorted every details.

GSoC2011(Week 9): boot ARM using coreboot to romstage

Hi all. Here I come again. With one week’s work, coreboot now can add romstage to the romfile, pass control to the romstage and find ramstage. I add a new way using a binary file to add stage to a rom file. Since I have not got an idea of how to store the hardware information, no hardware initialization is done now except the console. Following I will show you some snapshots:
This is a romfile without ramstage so it hangs at finding it:

This is a romfile with a simple ramstage. The ramstage code only sends a string “Hello ARM!” to the console then hangs there. It is compressed using LZMA in the romfile and should be decompressed and copied to the RAM at address 0x5000. This romfile is for testing the decompress function and move-jump function.

Next week, I will work on the ramstage. It is one of the hardest parts since we will deal with the hardware information. I need to design it and implement it. I want my code to be tested and reviewed early for that it is not only about implementation but also design. One could change an implementation with a low cost but couldn’t change a design with a low cost.
Thanks to God and Thanks to all the coreboot developers. Working with you all is so happy and fantastic!

GSoC 2011: flashrom part 3 – Midterm Evaluation

in schools essays that stray away from topic are often graded strictly. if one applies similar principles to my gsoc work it would probably degrade to “satisfactory” or worse. when i submitted my application for gsoc, most of my time line consisted of reverse engineering tasks. the plan was to quickly implement hardware sequencing and start reversing some vendor tools to find out how they unlock the ME.

what really happened is something i think is at least as useful as working ME unlocking code: flashrom got an almost full-time maintainer. 😉
i am handling a big chunk of the daily work (support requests on the mailing list and on IRC, keeping our database of tested devices up to date etc.) and i try to fix all problems in flashrom that i become aware of. this has led to countless already accepted patches and many which are still not reviewed yet. Continue reading GSoC 2011: flashrom part 3 – Midterm Evaluation

GSoC2011 spice payload midterm report

My project mostly involves to build an image with a small linux systemrunning a spice client, the system is attached  with/as a LAB tocoreboot.

What was done

My buildrom tree received some updates and small changes to the building system. The bigest problem to solve was make it build coreboot with the new [k]build system. For that I changed build rom to incorporate the coreboot options so the user can configure every aspects of coreboot – all from buildrom menus. 🙂

For prototyping I used a chroot with a debian bootstrap(debootstrap), this surely doesn`t fit well to the project but I didn`t much attention for that, I thought I could leave it for second half – in the last days talking to my mentor I realized I should have paid more attention to the image things.

With a debootstrap I hacked I small script to package copy that root to my final image, what, once again, doesn`t fit our needs and requirements and here comes the tasks to be taken in the second half.

Second half

The project has been designed to be fully installed in/loaded from flash, It`s loaded with filo(but like discussed with my mentor any other bootload would fit prefectly).

Busybox will be our base system and a x-server. To acomplish that I have to take and finish the following tasks:

  • design the building strategies which involves;
    • building the busybox(well, this one is already done once we have a busybox package in buildrom system – I just need to base on that);
    • select the needed x-server componentes(modules – Xlibs, Xprogs, Xvesa);
    • select the alsa packages;
    • include the spice client and its dependencies;
  • define the kernel features;
  • define how filo is about to load the final image;
  • define the best compression algorithm;
  • integrate the whole thing to buildrom;
  • alix board support;

The base building scripts will be packaged separetely and then integrated to buildrom like the other packages(i.e busybox, filo, grub and so on).

There`re just 6 weeks to the final evaluation and I`m leaving the alix board support to the last 2 weeks.

The build scripts and kernel prototyping will take the 2 first weeks, while the third one I`ll be working to put everything to be built by buildrom, the system can be tested as a proper system from an iso image till I get to integrate it to buildrom and package it as a coreboot payload.

GSoC 2011: midterm report under panic

Well my progress is not so shiny as other students. Looks like I overestimated my capabilities in my project proposal. I ended up with long exam session, lurking by reading coreboot mailing list (like an old cow), reading stuff about computer architecture, making hardware tools and trying to understand how git works 🙂

Done some patches, unfortunately, nobody likes it 🙂

Temporary libpayload fixes for flashrom as a payload

Flashrom as a payload with usb flash drive support

SerialICE for coreboot

Triggering another payload

For the second half of GSoC:

I’m working on “carFlashrom” (Yep, sounds a bit french) project:

http://www.coreboot.org/pipermail/coreboot/2011-July/065902.html

If this project is possible, then flashing would be possible without working RAM.

I would like to receive some response to my mails in the list as I am confused with my project goals, what others do think? I need some alternative goal if this is not feasible.

Give me some thoughts.

 

Bonus for readers: this one might be used with flashrom as rayer_spi. Modify flashrom source according to pinout and bits of par port registers:

http://logix4u.net/Legacy_Ports/Parallel_Port/A_tutorial_on_Parallel_port_Interfacing.html

I used m74hc244 from ST, even though parport signals are 5V, the chip is working right with VCC 3.3V.

http://dev.frozeneskimo.com/resources/jtag_wiggler_clone

GSoC2011: midterm report

Hi all. Welcome to my midterm report for project “porting coreboot to ARM”.

Summary

The goal of this project is porting coreboot to ARM and taking advantage of coreboot’s strength in properly configuring PCI, SAS, SATA and SCSI devices; fast boot times; and payload support.

For ARM SOCs, the device configuring is much easier than that for X86. Most device controllers are connected through the on-chip bus. So the mainly work is focus on porting the basic layout and helping tools to ARM architecture, including CBFS, cbfstool and the codes helping loading next stage and payload into ram.

Changes to this project

At first, I want to work on Marvell ARM SOCs with PCIE support, but after checking into it, I found that mostly all the information and SDK of Marvell SOCs are covered under an NDA license. So I moved to VersatilePB from Armltd.

What works now

  • CBFS record the architecture information in the master header
  • cbfstool can detect the architecture of a rom file
  • cbfstool can create an ARM rom file with bootblock
  • bootblock for VersatilePB is ready for use
  • romstage code for VersatilePB has been written

What doesn’t work (yet)

  • cbfstool can not add-stage to the romfile due to a problem in prase_elf_to_stage
  • romstage for VersatilePB has not been tested
  • ramstage code for VersatilePB has not been written

What needs work

  • design the information struct of hardware for payload on ARM

In this week, I will try to fix the problem of add-stage on ARM and test the romstage code.
Got any feature suggestions/ideas ?