spice payload: Before MidTerm GSoC report

My very first task on gsoc was to make buildrom work with latest codes from coreboot, with that I changed how it used to build coreboot. First I introduced the coreboot kconfig options to buildrom so the user can configure and choose the options for coreboot in the same mainmenu as buildrom.

 
Some small changes was introduced as a consistent pattern to name the kernel mk files and the possibility to checkout source code with https:// or svn://.
Updated some packages mk files to comply some patterns I introduced.

 
I still have some changes to introduce but I think it`s already usable. I might push the final bits in the next few days whenever I get a chance to work out my patches.

GSoC 2011: flashrom + filo = ?

 

The answer is flashrom payload, which is capable flashing roms out of usb stick. If you use seabios, you will be able to choose to run this payload instead of booting os. It might be worth for payload developers if we would have a small payload for selecting other payloads out of CBFS 🙂

Patches are here. Sorry for weird stuff there 🙂

 

My GSOC project is not going well, I end up with problems almost everywhere 🙁 (Only the good thing is that my exams went well). I spend my time trying to understand what is going on. Yesterday I was running an overflowing code allmost all day, until I found out what is wrong… My E350M1 is still not working (coreboot doesn’t run with 512 kB chip). So I have ordered some chips from ebay. While I’m waiting I have made some PCB adapters to make a dual flash device. Also made additional PCB for RS232<->UART<->USB interface.

I would better go coding… Bye!

AMD contributes A-series Family 12 (Llano), Hudson-2 (SB900), and Torpedo mainboard

Frank Vibrans from AMD pushed commits for the Fam12 and SB900 code into gerrit last week. This is just days after the official A-series release. The review has started. Feel free to help out. The gerrit links are:

http://review.coreboot.org/#change,54

http://review.coreboot.org/#change,53

http://review.coreboot.org/#change,52

http://review.coreboot.org/#change,51

http://review.coreboot.org/#change,41

http://review.coreboot.org/#change,40

 

GSoC2011(Week 5): the layout of coreboot rom and cbfstool for ARM

Hi all. How time flies. It has been 4 weeks since my last post. During this month, I have finished the design and implement of bootblock, Rom structure and cbfstool for ARM. Following I will show my changes to you all.
Continue reading GSoC2011(Week 5): the layout of coreboot rom and cbfstool for ARM

GSoC 2011: flashrom part 2 – SFDP

SFDP (Serial Flash Discoverable Parameters) is a JEDEC standard for querying the capabilities of serial flash chips. This allows software like flashrom to support chips without having all properties hard-coded beforehand. SFDP is structured in tables which are laid out in their own linear address space (independent from the “normal” range used to access the stored data). Starting at address 0x0 a mandatory header begins with a signature 0x50444653 (or ‘S’, ‘F’, ‘D’, ‘P’ in ASCII) followed by versioning data and the number of parameter headers. These headers are 64b long and have fields for versioning data, identification, length and offset where the real stuff i.e. the parameter table resides. There is one mandatory table and up to 255 can be added optionally. In the current version of the standard (2011-04) only the mandatory table is defined, but vendors are free (and quite encouraged by the standard) to add their customized tables and from the few data sheets i have seen mentioning SFDP the vendors do that (see below).

I spare you from the nasty details, but keep in mind that the mandatory table allows to retrieve the following properties:

  • the total size of the device
  • 4 (unified) block erasers (size of erase blocks and associated opcode)
  • address mode (24b, 32b or both)
  • status register write enable (none, WREN or EWSR)
  • lots of fast read-related stuff (like modes supported and number of wait states/dummy cycles needed in each)

The good news is: this would be enough to allow flashrom to work with unknown (yet unreleased) chips without recompilation!

The even better news is: i have a patch for that 😉

The bad news: i am not sure if there exists any hardware that supports it yet. Continue reading GSoC 2011: flashrom part 2 – SFDP

GSoC 2011: (week 2) Coreboot Spice Payload

I still haven’t had a good progress on my project, my first step is to work around the buildrom system.

I got to bring fully the coreboot Kconfig options to buildrom, since I don’t want to manually update it after coreboot updates I decided to write a small program to parse the coreboot Kconfig files. I found some api’s to help but I god stuck with that first task since none of them actually help me so much. A simple task became so complex and took me more time than I wanted(I started to update the api’s and change it acordingly to my needs, but well my project is not a kconfig api).

For a better and simpler solution I sat down and wrote a small shell script to run all the Kconfig’s and merge it into a single Kconfig.coreboot.

Now the next task is to change the building flow, how coreboot is fetched, patched and built.

For the final image and package I still want to get it all on the flash, I’m working on finding a solution to fit it as small as possible.

I found it would be interesting to use Kdrive to make the image smaller since it’s a minimal X server, but it’s unmaintained and we can build a thin X server from upstream.
For code sharing and analisys I setup a git repository so my mentor can comment on what I’m writing.
Now I have to move I bit faster.

GSoC 2011: flashrom part 1 – Hardware Sequencing

Hey there!

My name is Stefan Tauner and I am the one GSoC student working on flashrom this summer. I live in Vienna/Austria where i am studying computer engineering since 2005 (almost done, I only need to find someone writing my thesis for me… should ask some politicians where they got their ghostwriters…).

Since I started playing around with flashrom and proposed my GSoC project in March I have been quite active in the small flashrom universe. The current main maintainers and contributers – Carl-Daniel Hailfinger, Stefan Reinauer and Michael Karcher – were all very busy and so i was drawn into handling the daily support with the help of other regulars (most outstandingly Idwer Vollering, thank you!). This proved to offer very good opportunities to dive into the code base to answer the questions of others and to get familiar with the overall design. It also led to numerous (mostly tiny) patches authored by me which can be viewed on our patchwork site.

Although I think this was all quite fruitful and also in the best interest of flashrom the main objective is something else: Add support to unlock flash regions on newer Intel chipsets. Many details can be read on the thread leading to my GSoC application here. In this post i will focus on a tiny related bit, that i have already implemented and is currently under review: Hardware Sequencing.

Two weeks ago I wrote a lengthy mail to our mailing list (which you certainly should follow if you are interested in our work!) about my plans to implement hardware sequencing for Intel chipsets and some related questions. You can read it at our mail archive site too, but i will republish it here almost in full (please forgive me the left out capitalization etc.). Continue reading GSoC 2011: flashrom part 1 – Hardware Sequencing

GSoC2011(Week 1): Analysis of U-boot ARM boot code

This is such a busy week. At the end of last week, I have just ordered my OpenRD-Ultimate box but sadly it will be delivered at the end of June. So if I just wait for that box, I will not be able to test my code. That’s terrible! After talking with my mentor, I decided first porting coreboot to RealView Versatile/PB926EJ-S board then to OpenRD-Ultimate. Since qemu can emulate PB926EJ-S, I can test my code on it quickly and freely. After this work, the basic layout, libs and headers for ARM are ready to use. So I can start to port coreboot to OpenRD-Ultimate then.
Continue reading GSoC2011(Week 1): Analysis of U-boot ARM boot code