GSoC2011 spice payload midterm report

My project mostly involves to build an image with a small linux systemrunning a spice client, the system is attached  with/as a LAB tocoreboot.

What was done

My buildrom tree received some updates and small changes to the building system. The bigest problem to solve was make it build coreboot with the new [k]build system. For that I changed build rom to incorporate the coreboot options so the user can configure every aspects of coreboot – all from buildrom menus. 🙂

For prototyping I used a chroot with a debian bootstrap(debootstrap), this surely doesn`t fit well to the project but I didn`t much attention for that, I thought I could leave it for second half – in the last days talking to my mentor I realized I should have paid more attention to the image things.

With a debootstrap I hacked I small script to package copy that root to my final image, what, once again, doesn`t fit our needs and requirements and here comes the tasks to be taken in the second half.

Second half

The project has been designed to be fully installed in/loaded from flash, It`s loaded with filo(but like discussed with my mentor any other bootload would fit prefectly).

Busybox will be our base system and a x-server. To acomplish that I have to take and finish the following tasks:

  • design the building strategies which involves;
    • building the busybox(well, this one is already done once we have a busybox package in buildrom system – I just need to base on that);
    • select the needed x-server componentes(modules – Xlibs, Xprogs, Xvesa);
    • select the alsa packages;
    • include the spice client and its dependencies;
  • define the kernel features;
  • define how filo is about to load the final image;
  • define the best compression algorithm;
  • integrate the whole thing to buildrom;
  • alix board support;

The base building scripts will be packaged separetely and then integrated to buildrom like the other packages(i.e busybox, filo, grub and so on).

There`re just 6 weeks to the final evaluation and I`m leaving the alix board support to the last 2 weeks.

The build scripts and kernel prototyping will take the 2 first weeks, while the third one I`ll be working to put everything to be built by buildrom, the system can be tested as a proper system from an iso image till I get to integrate it to buildrom and package it as a coreboot payload.

GSoC 2011: midterm report under panic

Well my progress is not so shiny as other students. Looks like I overestimated my capabilities in my project proposal. I ended up with long exam session, lurking by reading coreboot mailing list (like an old cow), reading stuff about computer architecture, making hardware tools and trying to understand how git works 🙂

Done some patches, unfortunately, nobody likes it 🙂

Temporary libpayload fixes for flashrom as a payload

Flashrom as a payload with usb flash drive support

SerialICE for coreboot

Triggering another payload

For the second half of GSoC:

I’m working on “carFlashrom” (Yep, sounds a bit french) project:

http://www.coreboot.org/pipermail/coreboot/2011-July/065902.html

If this project is possible, then flashing would be possible without working RAM.

I would like to receive some response to my mails in the list as I am confused with my project goals, what others do think? I need some alternative goal if this is not feasible.

Give me some thoughts.

 

Bonus for readers: this one might be used with flashrom as rayer_spi. Modify flashrom source according to pinout and bits of par port registers:

http://logix4u.net/Legacy_Ports/Parallel_Port/A_tutorial_on_Parallel_port_Interfacing.html

I used m74hc244 from ST, even though parport signals are 5V, the chip is working right with VCC 3.3V.

http://dev.frozeneskimo.com/resources/jtag_wiggler_clone

GSoC2011: midterm report

Hi all. Welcome to my midterm report for project “porting coreboot to ARM”.

Summary

The goal of this project is porting coreboot to ARM and taking advantage of coreboot’s strength in properly configuring PCI, SAS, SATA and SCSI devices; fast boot times; and payload support.

For ARM SOCs, the device configuring is much easier than that for X86. Most device controllers are connected through the on-chip bus. So the mainly work is focus on porting the basic layout and helping tools to ARM architecture, including CBFS, cbfstool and the codes helping loading next stage and payload into ram.

Changes to this project

At first, I want to work on Marvell ARM SOCs with PCIE support, but after checking into it, I found that mostly all the information and SDK of Marvell SOCs are covered under an NDA license. So I moved to VersatilePB from Armltd.

What works now

  • CBFS record the architecture information in the master header
  • cbfstool can detect the architecture of a rom file
  • cbfstool can create an ARM rom file with bootblock
  • bootblock for VersatilePB is ready for use
  • romstage code for VersatilePB has been written

What doesn’t work (yet)

  • cbfstool can not add-stage to the romfile due to a problem in prase_elf_to_stage
  • romstage for VersatilePB has not been tested
  • ramstage code for VersatilePB has not been written

What needs work

  • design the information struct of hardware for payload on ARM

In this week, I will try to fix the problem of add-stage on ARM and test the romstage code.
Got any feature suggestions/ideas ?

spice payload: Before MidTerm GSoC report

My very first task on gsoc was to make buildrom work with latest codes from coreboot, with that I changed how it used to build coreboot. First I introduced the coreboot kconfig options to buildrom so the user can configure and choose the options for coreboot in the same mainmenu as buildrom.

 
Some small changes was introduced as a consistent pattern to name the kernel mk files and the possibility to checkout source code with https:// or svn://.
Updated some packages mk files to comply some patterns I introduced.

 
I still have some changes to introduce but I think it`s already usable. I might push the final bits in the next few days whenever I get a chance to work out my patches.

GSoC 2011: flashrom + filo = ?

 

The answer is flashrom payload, which is capable flashing roms out of usb stick. If you use seabios, you will be able to choose to run this payload instead of booting os. It might be worth for payload developers if we would have a small payload for selecting other payloads out of CBFS 🙂

Patches are here. Sorry for weird stuff there 🙂

 

My GSOC project is not going well, I end up with problems almost everywhere 🙁 (Only the good thing is that my exams went well). I spend my time trying to understand what is going on. Yesterday I was running an overflowing code allmost all day, until I found out what is wrong… My E350M1 is still not working (coreboot doesn’t run with 512 kB chip). So I have ordered some chips from ebay. While I’m waiting I have made some PCB adapters to make a dual flash device. Also made additional PCB for RS232<->UART<->USB interface.

I would better go coding… Bye!

AMD contributes A-series Family 12 (Llano), Hudson-2 (SB900), and Torpedo mainboard

Frank Vibrans from AMD pushed commits for the Fam12 and SB900 code into gerrit last week. This is just days after the official A-series release. The review has started. Feel free to help out. The gerrit links are:

http://review.coreboot.org/#change,54

http://review.coreboot.org/#change,53

http://review.coreboot.org/#change,52

http://review.coreboot.org/#change,51

http://review.coreboot.org/#change,41

http://review.coreboot.org/#change,40

 

GSoC2011(Week 5): the layout of coreboot rom and cbfstool for ARM

Hi all. How time flies. It has been 4 weeks since my last post. During this month, I have finished the design and implement of bootblock, Rom structure and cbfstool for ARM. Following I will show my changes to you all.
Continue reading GSoC2011(Week 5): the layout of coreboot rom and cbfstool for ARM

GSoC 2011: flashrom part 2 – SFDP

SFDP (Serial Flash Discoverable Parameters) is a JEDEC standard for querying the capabilities of serial flash chips. This allows software like flashrom to support chips without having all properties hard-coded beforehand. SFDP is structured in tables which are laid out in their own linear address space (independent from the “normal” range used to access the stored data). Starting at address 0x0 a mandatory header begins with a signature 0x50444653 (or ‘S’, ‘F’, ‘D’, ‘P’ in ASCII) followed by versioning data and the number of parameter headers. These headers are 64b long and have fields for versioning data, identification, length and offset where the real stuff i.e. the parameter table resides. There is one mandatory table and up to 255 can be added optionally. In the current version of the standard (2011-04) only the mandatory table is defined, but vendors are free (and quite encouraged by the standard) to add their customized tables and from the few data sheets i have seen mentioning SFDP the vendors do that (see below).

I spare you from the nasty details, but keep in mind that the mandatory table allows to retrieve the following properties:

  • the total size of the device
  • 4 (unified) block erasers (size of erase blocks and associated opcode)
  • address mode (24b, 32b or both)
  • status register write enable (none, WREN or EWSR)
  • lots of fast read-related stuff (like modes supported and number of wait states/dummy cycles needed in each)

The good news is: this would be enough to allow flashrom to work with unknown (yet unreleased) chips without recompilation!

The even better news is: i have a patch for that 😉

The bad news: i am not sure if there exists any hardware that supports it yet. Continue reading GSoC 2011: flashrom part 2 – SFDP

GSoC 2011: (week 2) Coreboot Spice Payload

I still haven’t had a good progress on my project, my first step is to work around the buildrom system.

I got to bring fully the coreboot Kconfig options to buildrom, since I don’t want to manually update it after coreboot updates I decided to write a small program to parse the coreboot Kconfig files. I found some api’s to help but I god stuck with that first task since none of them actually help me so much. A simple task became so complex and took me more time than I wanted(I started to update the api’s and change it acordingly to my needs, but well my project is not a kconfig api).

For a better and simpler solution I sat down and wrote a small shell script to run all the Kconfig’s and merge it into a single Kconfig.coreboot.

Now the next task is to change the building flow, how coreboot is fetched, patched and built.

For the final image and package I still want to get it all on the flash, I’m working on finding a solution to fit it as small as possible.

I found it would be interesting to use Kdrive to make the image smaller since it’s a minimal X server, but it’s unmaintained and we can build a thin X server from upstream.
For code sharing and analisys I setup a git repository so my mentor can comment on what I’m writing.
Now I have to move I bit faster.