coreboot

New coreboot debugging solutions

Hello. I am Kyösti Mälkki and I will be working on improvements for coreboot debugging tools during my GSoC 2013. My GSoC project plan has some details on things to come, but deliverables and schedule there will be fine-tuned next week or so. All in all, my work here should make it a little less painful to port new mainboards to coreboot and make SerialICE use more flexible.

Some feedback I have already received and the discussion we had on #coreboot suggests that some ARM boards are good candidates to be used for debugging x86 targets. Keep tuned in, the success of my work depends heavily on getting test results from a variety of mainboards.

GSoC 2013 accepted coreboot projects announced

We are happy to announce the GSoC 2013 coreboot projects:

Congratulations and welcome to coreboot GSoC 2103.

Google Summer of Code 2013 (updated)

coreboot has been accepted to participate in Google Summer of Code, 2013.

coreboot has many Project Ideas for various firmware ability levels and the coreboot project also hosts flashrom and SerialICE projects. Please visit the wiki for additional information.

Support for Supermicro X7DB8+ added

It’s been a while since i committed the northbridge code for the Intel 5000 chipset. Now i finally had some spare time to clean up my Supermicro board patch. This board features:

Dual Socket 771
1 PCI-e x4 Slot
2 PCI-e x8 Slot
3 PCI-X Slots
Onboard Adaptec SCSI Controller
two Gigabit NICs
and of course various other I/O stuff like serial ATA, IDE, serial/parallel ports, etc

What isn’t working right now:

Fan Control. All Fans are running on full speed, support for the Winbond W83793 and PECI has to be added
using a PCI-e x1 graphics card. As soon as such a card is plugged in, the system dies with a Machine check exception during startup.
Automatic MPTABLE generation. I’m currently working on a generic solution, but for now you have to edit devicetree.cb manually.

coreboot at IDF 2012 Beijing

Come visit booth C26 at IDF 2012 in Beijing for a demonstration of the world’s first consumer available coreboot based laptop based on Intel’s Sandybridge processor.

Google releases Intel Sandybridge support for coreboot

Exciting times! In the last couple of days, Google has released a major piece of coreboot support for the Intel Sandybridge processor and Cougar Point southbridge. This is the first time that coreboot supports the latest generation of Intel chipsets. In the next weeks more code will be released to support a number of mainboards with this processor/chipset combination. Stay tuned!

Check out the article on Phoronix.

Flip Bits, Not Burgers – coreboot GSoC 2012 – Update

Update –

coreboot was not selected to participate in GSoC 2012. This is
disappointing new for the project. I do not know why we were not
selected this year. I will attend the post selection meeting to see
what we can do to improve our chances of selection next year.

Students, thank you for your interest in coreboot. We are happy that
you are engaging with our community. I hope that you continue
exploring your interest in coreboot. Please let us know what we can do
to assist you in your learning.

Feel free to send me questions, comments, or concerns.

Regards,
Marc

http://google-opensource.blogspot.com/

Continue reading Flip Bits, Not Burgers – coreboot GSoC 2012 – Update

Intel i5000 northbridge code commited

I’ve started that port in November 2011, and made it finally working in January. Well, at least working on my Supermicro X7DB8 Board. Compared to the vendor BIOS which takes about 30 seconds from power-on to grub, coreboot finishes the same task in 3s. Unfortunately the VGA BIOS takes about 2 seconds to program the register to do 80×25 resolution, so eventually we end up with 5s. If you don’t need a VGA console, and prefer a serial console, you can save even these two seconds.

Actually i didn’t expect the port progressing so fast. One tool that was a great help was serialice. I used it to watch the original BIOS initializing memory. To get serialice running, all you have to do is writing a few lines of board specific C code, which initializes the serial port and some basic chipset parts required for accessing the serial port registers. On the host side, a patched QEMU is running, executing the vendor BIOS while redirecting HW accesses to the target computer. Which HW accesses are redirected can be configured by a small lua script. LUA can also be used to pretty print the output from serialice.

Continue reading Intel i5000 northbridge code commited

Bifferboard porting

Ever heard about the bifferboard? It is a small RDC x86 SoC with 150MHz 486 compatible CPU, 8MB flash and 32MB RAM, ethernet and TTL serial line and a few GPIOs. It comes with very tiny loader called biffboot. Quite natural target for coreboot and u-boot. My flatmate purchased one but never had actually time to do anything with that so here it comes. Continue reading Bifferboard porting

Coreboot in shipping products

We are starting to see coreboot in more shipping products this summer and I expect even more in the fall. The exciting thing is that coreboot is becoming a piece of technology that vendors are starting to advertise. A recent example is the Portwell PCS-8277:

PORTWELL ANNOUNCES REVOLUTIONARY IN-VEHICLE PC
WITH THE BOOT SPEED OF AN APPLIANCE New PCS-8277 telematics system based on Coreboot® technology with HD graphics processing engine

I think that we are starting to see vendors and customers becoming more knowledgeable about what is going into their products and how coreboot is an advantage in many situations. I hope to see more announcements in the coming months.