Category: coreboot

Intel i5000 northbridge code commited

I’ve started that port in November 2011, and made it finally working in January. Well, at least working on my Supermicro X7DB8 Board. Compared to the vendor BIOS which takes about 30 seconds from power-on to grub, coreboot finishes the same task in 3s. Unfortunately the VGA BIOS takes about 2 seconds to program the register to do 80×25 resolution, so eventually we end up with 5s. If you don’t need a VGA console, and prefer a serial console, you can save even these two seconds.

Actually i didn’t expect the port progressing so fast. One tool that was a great help was serialice. I used it to watch the original BIOS initializing memory. To get serialice running, all you have to do is writing a few lines of board specific C code, which initializes the serial port and some basic chipset parts required for accessing the serial port registers. On the host side, a patched QEMU is running, executing the vendor BIOS while redirecting HW accesses to the target computer. Which HW accesses are redirected can be configured by a small lua script. LUA can also be used to pretty print the output from serialice.

Continue reading Intel i5000 northbridge code commited

Coreboot in shipping products

We are starting to see coreboot in more shipping products this summer and I expect even more in the fall. The exciting thing is that coreboot is becoming a piece of technology that vendors are starting to advertise. A recent example is the Portwell PCS-8277:

PORTWELL ANNOUNCES REVOLUTIONARY IN-VEHICLE PC
WITH THE BOOT SPEED OF AN APPLIANCE New PCS-8277 telematics system based on Coreboot® technology with HD graphics processing engine 

I think that we are starting to see vendors and customers becoming more knowledgeable about what is going into their products and how coreboot is an advantage in many situations. I hope to see more announcements in the coming months.

Flashrom 0.9.4 released – Flashing BIOS/ROM chips from the Unix/Linux command line using various programmers

flashrom logo

Forgot to mention this here: We released flashrom 0.9.4 a few days ago, the latest release of the open-source, GPL'd ROM chip flashing software for Linux, *BSD, DOS, and partially also Windows (work in progress, though).

Here's a quick summary of the release announcement. Some of the noteworthy news items include:

  • Support for new programmers: OpenMoko Neo1973/Neo FreeRunner debug board version 2 or 3, Olimex ARM-USB-TINY, ARM-USB-TINY-H, ARM-USB-OCD, and ARM-USB-OCD-H, Open Graphics Project development card (OGD1), Angelbird Wings PCIe SSD/88SX7042, ITE IT85xx embedded controllers, Intel NICs with parallel flash.
  • Dozens of added flash chips, chipsets, mainboards.
  • Improved Dediprog SF100 support.
  • Add support for more than one Super I/O or EC per machine.
  • Always read the flash chip before writing, for improved error checking and faster programming.
  • Enable write support on NVIDIA MCP6x/MCP7x.
  • Lots of bugfixes, documentation fixes, internal improvements, etc.

Get the latest release tarball, or download and build the most recent version via Subversion:

  $ svn co svn://flashrom.org/flashrom/trunk flashrom
  $ cd flashrom
  $ make

I already updated the Debian package to 0.9.4 (it has also already migrated to Debian testing and Ubuntu), other people have updated Fedora, Gentoo, NetBSD etc. etc.

There's already a huge amount of patches queued for the next release, including support for even more programmers, PowerPC support (tested on Mac Mini and others), and of course the usual "more boards, more chips" items...

GSoC 2011: little trip

This might be not a good idea, but I had got bored with my project not going well, so I eventually got on trip, through “FOSS and friends” 🙂 I have had some headache with nouveau driver, till I understood that deprecated version was installed. Tried to install a package, which got me in a geometric progression of required dependency packages 🙂 I have filed a bug for LibreOffice, and got one future TODO for “reverse enginering” how exactly CUPS works with one of the label printers we have here as it needs a slight modification. The best thing I have done is started reading a book and building “Linux From Scratch (LFS)”. It’s great while building a package you are accompanied with a short page of info about it, not all manual 🙂 Also I have found out that I don’t have good stuff to read, except that 1k pages book about Linux internals 🙂 While looking at the freenode chatrooms list I have found this resource about c language: http://www.iso-9899.info – all it needs is time for reading everything 🙂

 

My project progress is really slow. As Marc suggested I have done some work to reduce stack usage: wrapped functions to read and use file by 256B peaces (somewhat default granularity). But that still needs testing and cleaning up. Also I need to cleanup my previous work that I haven’t submitted to the list, which enabled running code in car (even though not completely working, as mtrr settings might be wrong or more problems still there).

GSoC2011: coreboot spice payload, OE and rootfs

As stated in my midterm report I’m working this first 2 weeks after midterm to work on building the payload image. I wanted to hardcode everything but we(my mentor and I) understood it would be better to use something like OpenEmbedded for that.

 
This first week I studied OpenEmbedded. I tested many distributions starting with angstrom, they showed too heavy for our purpose. After those tests I found micro and realized it would be a better start.

 
With that I’m working around micro to build our own distro, I’m adding X11 dependencies and right now I’m packing the spice client and its dependencies. In the end of the week I must have sorted every details.

GSoC2011(Week 9): boot ARM using coreboot to romstage

Hi all. Here I come again. With one week’s work, coreboot now can add romstage to the romfile, pass control to the romstage and find ramstage. I add a new way using a binary file to add stage to a rom file. Since I have not got an idea of how to store the hardware information, no hardware initialization is done now except the console. Following I will show you some snapshots:
This is a romfile without ramstage so it hangs at finding it:

This is a romfile with a simple ramstage. The ramstage code only sends a string “Hello ARM!” to the console then hangs there. It is compressed using LZMA in the romfile and should be decompressed and copied to the RAM at address 0x5000. This romfile is for testing the decompress function and move-jump function.

Next week, I will work on the ramstage. It is one of the hardest parts since we will deal with the hardware information. I need to design it and implement it. I want my code to be tested and reviewed early for that it is not only about implementation but also design. One could change an implementation with a low cost but couldn’t change a design with a low cost.
Thanks to God and Thanks to all the coreboot developers. Working with you all is so happy and fantastic!

GSoC2011 spice payload midterm report

My project mostly involves to build an image with a small linux systemrunning a spice client, the system is attached  with/as a LAB tocoreboot.

What was done

My buildrom tree received some updates and small changes to the building system. The bigest problem to solve was make it build coreboot with the new [k]build system. For that I changed build rom to incorporate the coreboot options so the user can configure every aspects of coreboot – all from buildrom menus. 🙂

For prototyping I used a chroot with a debian bootstrap(debootstrap), this surely doesn`t fit well to the project but I didn`t much attention for that, I thought I could leave it for second half – in the last days talking to my mentor I realized I should have paid more attention to the image things.

With a debootstrap I hacked I small script to package copy that root to my final image, what, once again, doesn`t fit our needs and requirements and here comes the tasks to be taken in the second half.

Second half

The project has been designed to be fully installed in/loaded from flash, It`s loaded with filo(but like discussed with my mentor any other bootload would fit prefectly).

Busybox will be our base system and a x-server. To acomplish that I have to take and finish the following tasks:

  • design the building strategies which involves;
    • building the busybox(well, this one is already done once we have a busybox package in buildrom system – I just need to base on that);
    • select the needed x-server componentes(modules – Xlibs, Xprogs, Xvesa);
    • select the alsa packages;
    • include the spice client and its dependencies;
  • define the kernel features;
  • define how filo is about to load the final image;
  • define the best compression algorithm;
  • integrate the whole thing to buildrom;
  • alix board support;

The base building scripts will be packaged separetely and then integrated to buildrom like the other packages(i.e busybox, filo, grub and so on).

There`re just 6 weeks to the final evaluation and I`m leaving the alix board support to the last 2 weeks.

The build scripts and kernel prototyping will take the 2 first weeks, while the third one I`ll be working to put everything to be built by buildrom, the system can be tested as a proper system from an iso image till I get to integrate it to buildrom and package it as a coreboot payload.

GSoC 2011: midterm report under panic

Well my progress is not so shiny as other students. Looks like I overestimated my capabilities in my project proposal. I ended up with long exam session, lurking by reading coreboot mailing list (like an old cow), reading stuff about computer architecture, making hardware tools and trying to understand how git works 🙂

Done some patches, unfortunately, nobody likes it 🙂

Temporary libpayload fixes for flashrom as a payload

Flashrom as a payload with usb flash drive support

SerialICE for coreboot

Triggering another payload

For the second half of GSoC:

I’m working on “carFlashrom” (Yep, sounds a bit french) project:

http://www.coreboot.org/pipermail/coreboot/2011-July/065902.html

If this project is possible, then flashing would be possible without working RAM.

I would like to receive some response to my mails in the list as I am confused with my project goals, what others do think? I need some alternative goal if this is not feasible.

Give me some thoughts.

 

Bonus for readers: this one might be used with flashrom as rayer_spi. Modify flashrom source according to pinout and bits of par port registers:

http://logix4u.net/Legacy_Ports/Parallel_Port/A_tutorial_on_Parallel_port_Interfacing.html

I used m74hc244 from ST, even though parport signals are 5V, the chip is working right with VCC 3.3V.

http://dev.frozeneskimo.com/resources/jtag_wiggler_clone